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2,375 Views
Registered: ‎10-02-2018

generic package support in Vivado

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I am porting a design to Xilinx, but run into a lot of unsupported features of VHDL in Vivado.

 

This whole design I am porting is based on generic package declarations, so this error is very disconcerting:

 

          The "Vhdl 2008 Package Instantiation Declaration" is not supported yet for simulation

 

How do folks deal with feature shortcomings of the Xilinx toolchain? In particular, how do folks maintain multiple source code trees to work around Xilinx's lack of support of the VHDL standard?

 

 

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Scholar richardhead
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2,360 Views
Registered: ‎08-01-2012

Re: generic package support in Vivado

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Write your synthesisable code with features that are supported (which isnt a lot).

Use an external simulator for testbenches.

 

If you have synthesisable 2008 code that needs to work on Xilinx, you'll need to modify the code to basically be '93 code. Otherwise dont use Xilinx.

 

Xilinx have pretty much dropped any plans to improve VHDL support. Dont expect better 2008 support any time soon. (BTW, I dont think any simulator has full 2008 feature support yet - but they got most of it)

18 Replies
Scholar richardhead
Scholar
2,361 Views
Registered: ‎08-01-2012

Re: generic package support in Vivado

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Write your synthesisable code with features that are supported (which isnt a lot).

Use an external simulator for testbenches.

 

If you have synthesisable 2008 code that needs to work on Xilinx, you'll need to modify the code to basically be '93 code. Otherwise dont use Xilinx.

 

Xilinx have pretty much dropped any plans to improve VHDL support. Dont expect better 2008 support any time soon. (BTW, I dont think any simulator has full 2008 feature support yet - but they got most of it)

Scholar drjohnsmith
Scholar
2,338 Views
Registered: ‎07-09-2009

Re: generic package support in Vivado

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Personally

 

I push xilinx to support VHDL more, a loosing battle,

 

design to a lowest common set of vhdl that I know works across all the tools I use.

 

Use external simulators where I can ,

 

 If I need to use little supported code, I try to isolate it.

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
2,321 Views
Registered: ‎10-02-2018

Re: generic package support in Vivado

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Thank you for the level set. This code base comes from an ASIC design, so the external simulator approach is well established

 

Very disappointing to hear that a $2.5B company can't be bothered by its customers.....

Scholar richardhead
Scholar
2,304 Views
Registered: ‎08-01-2012

Re: generic package support in Vivado

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@stillwatertheo

 

I think the majority of customers are using Verilog and System Verilog. That seems to be the focus from Xilinx. They are well behind on SV support as well, so VHDL just falls by the wayside.

Scholar brimdavis
Scholar
2,284 Views
Registered: ‎04-26-2012

Re: generic package support in Vivado

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@richardhead  "I think the majority of customers are using Verilog and System Verilog."

 

In spite of years of substandard, poorly tested, and badly documented VHDL language support in Vivado, and Xilinx's Verilog-only IP policy, the 2016 Wilson Research Group FPGA language usage survey showed the following:

  VHDL: 62%  Verilog: 55%   SystemVerilog: 21%   C/C++: 16%   SystemC: 5%
  ( inclusive, hence the sum > 100% )

 

>

> That seems to be the focus from Xilinx.

>

Instead of properly supporting their existing customer base, Xilinx's reconfigurable-computing-and-HLS-obsessed management appears to have offshored the Synthesis and Simulation tools to an underfunded group with little experience and poor language verification skills.
 

I have no objection to Xilinx developing new HLS tool flows, but throwing the majority of their current customers under the bus by neglecting the synthesis/simulation tool flow needed by their customer base is absurd (not to mention the lack of Vivado support for still-in-use S6/V6 device families).

 

-Brian

Scholar drjohnsmith
Scholar
2,273 Views
Registered: ‎07-09-2009

Re: generic package support in Vivado

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I think its getting to the edges of off topic,

 

in my experience, but the big guys use verilog, and version there of, 

    particularly in USA, 

 

so Xilinx are 'just' like others supporting the money, 

   which as a consultant I can't really dis agree with, 

 

but it still riles me

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Scholar brimdavis
Scholar
2,256 Views
Registered: ‎04-26-2012

Re: generic package support in Vivado

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2,219 Views
Registered: ‎10-02-2018

Re: generic package support in Vivado

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@brimdavis  yep, super frustrating and creating significant additional development cost to Xilinx customers. When an organization is not motivated by requests by its customers for features and fixes, it clearly creates an environments where brand loyalty is negative.

 

As there are plenty of examples of organizations that do treat their customers with respect, this does not reflect positively on the strength and conviction of Xilinx executive management. 

Observer dbanks122
Observer
1,453 Views
Registered: ‎12-06-2018

Re: generic package support in Vivado

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This is sad.... Such powerful features, it is a shame that Xilinx would choose not to support them. I require this VHDL-2008 generic package feature and this lack of support will create a lot of problems for me.

Scholar richardhead
Scholar
1,426 Views
Registered: ‎08-01-2012

Re: generic package support in Vivado

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@dbanks122 

Is there any particular reason you need generic packages? Afaik, Intel only just supported the feature recently, and only in the PRO verison for newest top end devices.

While generic packages have very good useage in simulation, I dont really see too much benefit for synthesis, or at least nothing that cannot be worked around in '93 VHDL.

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Observer dbanks122
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1,411 Views
Registered: ‎12-06-2018

Re: generic package support in Vivado

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@richardhead I can surely work around it, but what could be just a few lines of code will end up being a whole lot of unnecessary duplication. Also note that Intel's PRO tool is not just a tool version for top end devices. It is really an entirely different tool than STANDARD and is ultimately meant to replace it. That being said, it has its own limitations and is a relatively immature tool. I hope that Xilinx/Vivado (which is definitely my preferred tool) will work to support powerful features like this and encourage its users to stay on the cutting edge.

Scholar richardhead
Scholar
1,401 Views
Registered: ‎08-01-2012

Re: generic package support in Vivado

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VHDL 2008 is hardly cutting edge. VHDL 2018 has just been standardised and starting to get support from Aldec (Like VHDL 2008, most features are aimed at better simulation)

Xilinx really are the last to the party, and have really neglected VHDL. But are finally getting soome support done. Currently Synthesis has better VHDL 2008 support than simulation.

Im still yet to see any real use for package generics for synthesis. Maybe you can provide an example?

Observer dbanks122
Observer
1,357 Views
Registered: ‎12-06-2018

Re: generic package support in Vivado

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@richardheadI have a design where entities A and B both use a type T from package P to define their ports. T as well as logic inside A and B use constant C which is also defined defined in package P (see simplified code below).

Now, A and B are part of a larger design. Lets call it Testbench for now. I want two variations of Testbench. One that uses C=1 and another that uses C=2. I want to accomplish this such that both designs/variations can coexist and be built within the same source tree without making modifications to the source for A, B and P.

In VHDL-2008, C could instead be a generic of package P. It would also be a generic of A and B. Then, Testbench could define its own generic and use it when instantiating A and B. A and B would in turn instantiate package P using that generic.

This way, Testbench can have 2+ variations, each one would be exactly the same but would pass a different generic down into A, B and P.

Consider another very Vivado-style use-case:

This case is similar to the above example, but instead of a VHDL Testbench, we have a Vivado BlockDesign. BlockDesign has blocks A and B. I want to be able to double click on these blocks and change generic C. The issue, is that even if C is a generic of A and B, there is no way for this constant's value to propagate down into package P, as far as I can tell, without generic packages.

 

Here is some massively simplified code for A, B, P and Testbench:

package P is
  constant C : natural := 1;
  constant A : natural := 1;
  type T is array (0 to A-1) of std_logic_vector(C-1 downto 0);
end package P;

-- In a separate VHDL file -- A and B are the same but with opposite data port directions entity A is generic ( C : natural := 1 ); port ( clk : in std_logic; data : in T ); end A; architecture RTL of A is begin -- uses C
... end RTL;

-- In a separate VHDL file
entity Testbench is
generic (
C : natural := 1;
);
end Testbench;
architecture TB of Testbench is
...
begin
A_i : entity A
generic map (
C => C
)
port map (
...
...
);

B_i : entity B
generic map (
C => C
)
port map (
...
...
);

end TB;

 

Once again, this is a largely simplified version of my design. I want to avoid code duplication as much as possible. I also (as mentioned above) would like to be able to use different configurations of the package P and type T by setting A and B's generics in a block design.

 

Thanks.

Scholar drjohnsmith
Scholar
1,354 Views
Registered: ‎07-09-2009

Re: generic package support in Vivado

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Doing logic, I could just get around things using nand gates.

But I'd rather use the tools to make my life easier.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Scholar richardhead
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1,337 Views
Registered: ‎08-01-2012

Re: generic package support in Vivado

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@dbanks122 

Your example doesnt really show much, and certainly doesnt show a use case for VHDL 2008. In your example you could simply provide C as a generic to the testbench which would filter down to A and B. No need for a package generic. 

If you're in ActiveHDL or Modelsim (and likely vivado) you can simply provide the generic in your scripts with -gC=1 or -gC=2 (or have it in a config file so the same test run script can be passed a test parameter on the command line)

So you have one script for test1 and another for test2. This is acheivable with VHDL '93 with your example.

VIvado does currently support unconstrained types from VHDL 2008, plus it supports the '93 feature of unconstrained ports (which get a size when connected). So you could easily do this:

 

 

package p is
  type t is array(natural range <>) of std_logic_vector; -- 2008 unconstrained type - supported by Vivado
end package p;

entity ent_A is
  port (
    port0 : in  t;  -- note - no sizes constrained in port definition
port1 : out t -- out ports can be unconstrained too ); .... TESTBENCH signal port0_sig : t(0 to C-1)(ww-1 downto 0);
signal port1_sig : t(0 to C+1)(ww-1 downto 0); inst : ent_a port map ( port0 => port0_sig, port1 => port1_sig ); -- port0 is now sized from port0_sig

 

 

Observer dbanks122
Observer
1,277 Views
Registered: ‎12-06-2018

Re: generic package support in Vivado

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@richardheadthank for this response. This will likely prove very useful to me. Is there a way for me to use unconstrained types for more complex record types like the following?

package p is
  type rec_type is record
    data : std_logic_vector(DATA_WIDTH-1 downto 0);
    enable : std_logic;
    ...
    mty : std_logic_vector(EMPTY_WIDTH-1 downto 0);
  end record rec_type;

  type rec_type_arr is array (natural range <>) of rec_type;
end package p;

I want DATA_WIDTH and EMPTY_WIDTH to be generics of the A and B (used for their ports). Is there some way for me to make data and mty unconstrained here?

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Observer dbanks122
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Registered: ‎12-06-2018

Re: generic package support in Vivado

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It looks like I can do something like:

entity ent_A is
  generic (
    NUM_LANES : natural := 2;
    DATA_WIDTH : natural := 64;
    EMPTY_WIDTH: natural := 3
  );
  port (
    port0 : in  rec_type_arr(0 to NUM_LANES-1)(data(DATA_WIDTH-1 downto 0),
                                               mty(EMPTY_WIDTH-1 downto 0));
    port1 : out rec_type_arr(0 to NUM_LANES-1)(data(DATA_WIDTH-1 downto 0),
mty(EMPTY_WIDTH-1 downto 0)) ); ... ...

I have not tried to synthesize this yet, but I saw an example similar to this at https://forums.xilinx.com/t5/Synthesis/VHDL-2008-unconstrained-array-of-record-containing-unconstrained/m-p/745372/highlight/true#M20599

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Scholar richardhead
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1,265 Views
Registered: ‎08-01-2012

Re: generic package support in Vivado

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@dbanks122 

I am basically doing exactly that in Vivado 2018.2, and its working just fine (for synthesis)

Its so much nicer being able to send an entire AXI4 bus (or arrays of them) in just two signals.

 

subtype mem_m2s_array_t is axi4_m2s_array_t(open)( awaddr( 31 downto 0), wdata(127 downto 0), wstrb(15 downto 0), araddr(31 downto 0) );
subtype mem_s2m_array_t is axi4_s2m_array_t(open)( rdata(127 downto 0) );

signal mem_m2s : mem_m2s_array_t(1 downto 0) := ( others => MEM_2110_M2S_DEFAULT );
signal mem_s2m : mem_s2m_array_t(1 downto 0) := ( others => MEM_2110_S2M_DEFAULT );

 

Btw, there is currently a bug where if any element is set as a null array, it removes the entire record:

https://forums.xilinx.com/t5/Synthesis/VHDL-Bug-Report-Vivado-Removes-non-null-port/td-p/847233