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Observer pev.hall
Observer
3,994 Views
Registered: ‎01-26-2009

glbl.v is not being loaded in my testbench

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Hello,

I'm trying to simulate a Verilog module inside my VHDL project. However the glbl.v does not appear to be loaded.

I'm currently using ISE 13.4. This did no appear to be a problem in 13.2. I'm currently in the process

Running: C:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o C:/work/.../ise/toplevel_tb_isim_beh.exe -prj C:/work/.../ise/toplevel_tb_beh.prj work.toplevel_tb work.glbl

You can see that work.glbl is being referenced in the command. If I have got the option selected to load it.

ERROR:HDLCompiler:71 - "N:/O.87xd/rtf/verilog/src/unisims/RAMB36SDP.v" Line 204: GSR is not declared under prefix glbl

ERROR:Simulator:777 - Static elaboration of top level VHDL design unit toplevel_tb in library work failed

 

Thanks,

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1 Solution

Accepted Solutions
Observer pev.hall
Observer
4,733 Views
Registered: ‎01-26-2009

Re: glbl.v is not being loaded in my testbench

Jump to solution

I've found a work around. Creating a verilog module that is one level higher then my test bench like so

 

--------------------------------------

module test;
    toplevel_tb tb_inst(
    );
endmodule
--------------------------------------

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1 Reply
Observer pev.hall
Observer
4,734 Views
Registered: ‎01-26-2009

Re: glbl.v is not being loaded in my testbench

Jump to solution

I've found a work around. Creating a verilog module that is one level higher then my test bench like so

 

--------------------------------------

module test;
    toplevel_tb tb_inst(
    );
endmodule
--------------------------------------

0 Kudos