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Scholar ronnywebers
Scholar
1,087 Views
Registered: ‎10-10-2014

have a signal change at a specific (absolute) simulation time (in a testbench)

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Is it possible to set a signal (in a testbench) at a specific (absolute) simulation time, something like this :

 

    abs_time : process
    begin
        enable <= '0';
        wait until time = 500ns;
        report "enabling system at sim time = 500ns";
        enable <= '1';
        wait;
    end process;

I get the error ' ERROR: [VRFC 10-53] time is illegal in an expression;

 

ooks like  it's not possible this way, but maybe by using some other construct, this can be mimic'd?

 

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Scholar richardhead
Scholar
1,664 Views
Registered: ‎08-01-2012

Re: have a signal change at a specific (absolute) simulation time (in a testbench)

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also, did you know you can combine all of these things?

 

process
begin
  enable <= '1', '0' after 100 ns, '1' after 200 ns;
  wait until some_event for 500 ns;
  assert (some_event) report "some_event didnt happen in the 500 ns time window" severity failure;

  report "Everything was goood"
wait; end process;
5 Replies
Moderator
Moderator
1,077 Views
Registered: ‎09-15-2016

Re: have a signal change at a specific (absolute) simulation time (in a testbench)

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Hi @ronnywebers

 

'time' is vhdl data type and 'wait until' is applied on condition and condition is applied on signals which is evaluated to true. Hence the reason of the error. May be you can declare a signal clk and apply this syntax as below:

wait until clk=500 ns;

 

Regards

Rohit

Regards
Rohit
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Scholar richardhead
Scholar
1,060 Views
Registered: ‎08-01-2012

Re: have a signal change at a specific (absolute) simulation time (in a testbench)

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@thakurr

That wont work - you cannot wait until some single = 500 ns.

 

you use:

 

wait for 500 ns;

Scholar richardhead
Scholar
1,665 Views
Registered: ‎08-01-2012

Re: have a signal change at a specific (absolute) simulation time (in a testbench)

Jump to solution

also, did you know you can combine all of these things?

 

process
begin
  enable <= '1', '0' after 100 ns, '1' after 200 ns;
  wait until some_event for 500 ns;
  assert (some_event) report "some_event didnt happen in the 500 ns time window" severity failure;

  report "Everything was goood"
wait; end process;
Moderator
Moderator
1,036 Views
Registered: ‎05-31-2017

Re: have a signal change at a specific (absolute) simulation time (in a testbench)

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HI @ronnywebers,

 

In support to @richardhead suggestions, The wait until statement suspends the process until a change occurs on any of the signals in the statement . It is mainly applied to check the condition of the signals and it cannot be applied to delay the process by some time. In your scenario, you have used the below statement which is not valid. You can use the statement wait for 500ns to delay the process.

wait until time = 500ns;

 

Thanks & Regards,
A.Shameer.

Scholar ronnywebers
Scholar
987 Views
Registered: ‎10-10-2014

Re: have a signal change at a specific (absolute) simulation time (in a testbench)

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thanks @richardhead, think that comes closest to what I like to achieve. I didn't know it could be combined that way, so thanks!

 

The other solution I saw was to use 'wait for ...' in between the signal assignments, but that requires recalculating all the relative delays between events each time I need other absolute time events. 

 

Your approach is more easy!

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