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alangford
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Registered: ‎06-15-2017

having difficulties with vhdl qualified expression and and assert statement

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Hi,

 

I want to add an assert statement to my VHDL testbench, with which Im using the Vivado 2017.2 xsim simulator

 

I want to assert if a counter exceeds a maximum value defined in a constant:

 

constant C_MAX : integer := 100;

signal cntr : unsigned(7 downto 0);

....

assert  cntr < to_unsigned(C_MAX,8)

  report "some message" severity Warning;

 

When I run the simulation, the assert fires because of the uninitialised value of the counter, i.e. cntr = "UUUUUUUU"

 

    I know I can fix this by including an initial value when I declare the cntr signal

i.e. signal cntr : unsigned(7 downto 0) := (others => '0');

 

I can also fix it by including the uninitialised value in the assert condition:

i.e. assert  cntr(0) = 'U' or cntr < to_unsigned(C_MAX,8)

 

    But I want this to work for the whole cntr vector rather than just the zeroth element by using a qualified expression:

assert  cntr = unsigned'(others => 'U') or cntr < to_unsigned(C_MAX,8)

 

Im not 100% sure if this is legal syntax, as this results in an XSIM [43-3294] EXCEPTION_ACCESS_VIOLATION

 

Can anyone suggest what's wrong with this syntax?

 

Thanks

               

 

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alangford
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Registered: ‎06-15-2017

thanks @geoffbarnes ... clearly this one had you scratching your head too!

 

casting to slv fixed the problem for me with xsim ... 

 

Thanks for your help with this!

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geoffbarnes
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Registered: ‎09-07-2011

Looks legal, but others might not be ok in this context.     Maybe try :     assert cntr = (cntr'range => 'U') .....

 

 

 

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alangford
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Registered: ‎06-15-2017

thanks for your suggestion @geoffbarnes ... I had however already tried this.

 

however, while the xsim compile and elaborate doesnt barf at this syntax, it doesnt actually result in the behaviour I need, i.e. when the sim starts, and cntr has its uninitialised value of "UUUUUUUU", the assert still fires, even though logically the expression cntr = (cntr'range => 'U') is true at this time.

 

oddly, even cntr(7 downto 0) = "UUUUUUUU" also gives the same behaviour, whereas cntr(0) = 'U' works just fine

 

It seems the test with the whole vector doesnt get interpreted correctly

 

Im just curious about the correct syntax, as I have a workaround

 

Thanks

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geoffbarnes
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Registered: ‎09-07-2011

Oh I see.     Tried this with modelsim.   Looks like the unsigned  "=" fails due to the meta-value, whereas the std_logic_vector "=" is fine.   This must just be the intended behavior of numeric_std.

 

library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;

entity foo is
    port ( a : in unsigned(0 to 10) := (others => 'U') );
begin
    assert a                   = (a'range => 'U') report "***Vector***"     severity failure;
    assert std_logic_vector(a) = (a'range => 'U') report "***Vector SLV***" severity failure;
    assert a(0)                = 'U'              report "***Bit***"        severity failure;
end entity;

architecture rtl of foo is
begin
end architecture;

 

 

Got this:

 

# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
#    Time: 0 ns  Iteration: 0  Instance: /foo
# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
#    Time: 0 ns  Iteration: 0  Instance: /foo
# ** Failure: ***Vector***
#    Time: 0 ns  Iteration: 0  Process: /foo/line__8#0 File: foo.vhd
# Break in Architecture rtl at foo.vhd line 8
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alangford
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Registered: ‎06-15-2017

thanks @geoffbarnes ... clearly this one had you scratching your head too!

 

casting to slv fixed the problem for me with xsim ... 

 

Thanks for your help with this!

View solution in original post

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