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Visitor
Visitor
4,460 Views
Registered: ‎01-17-2012

how get a faster simulation

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Hi,

I would like to know how could i get a faster simulation. My unit consit of a clock 50mhz that blink the led at every seconds.

 

I try to remove debug, to change the resolution but it doesn't seem to go faster... 10ns resolution take as long as 1ps ..

 

( fuse fds -o niksim.exe -timeprecision_vhdl 10ns -nodebug )

 

I'm using ISE 13.3.

 

test bench :

....

--------------------------------------------------------------------------

   constant CLK_period : time := 20 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: top PORT MAP (
CLK => CLK,
CLK_AUX0 => CLK_AUX0,
CLK_AUX1 => CLK_AUX1,
CLK_AUX2 => CLK_AUX2,
CLK_AUX3 => CLK_AUX3,
IO => IO,
INPUT => INPUT,
CS => CS,
MOSI => MOSI,
SCLK => SCLK,
DIN => DIN,
CTS => CTS,
TXD => TXD,
RXD => RXD,
DTR_RTS => DTR_RTS
);

-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;

--------------------------------------------------------------------------

 

device:

-------------------------------------------------------------------------

architecture Behavioral of top is

begin
--avoid error -> unrouted Output
IO(110 downto 1)<="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
process(CLK)
variable count : integer:=0;

begin
if(CLK'event and CLK='1') then
count:=count+1;
if( count=50000000) then
IO(0)<='1';
elsif(count=100000000) then
IO(0)<='0';
count:=0;
end if;
end if;
end process;

end Behavioral;

 

-----------------------------------------------------------

 

 

thank you for your help

 

-Nik-



 

 

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Highlighted
Professor
Professor
5,789 Views
Registered: ‎08-14-2007

First, simulation resolution makes very little difference in speed for modern simulators.

 

Second, as mentioned, the best way is to simulate a shorter counter.  Here's a trick

I picked up from comp.arch.fpga for automatically using smaller counts during simulation:

 

if( count=50000000

-- synthesis translate_off

 / 1000000

-- synthesis translate_on

) then
IO(0)<='1';
elsif(count=100000000

-- synthesis translate_off

 / 1000000

-- synthesis translate_on

) then

 

In this case for simulation, but not synthesis, divide the constants by 1 million.

Then when you go to synthesize you still get the longer counts and don't need

to remember to take the "simulation stuff" out of the design.

 

-- Gabor

-- Gabor

View solution in original post

3 Replies
Highlighted
Scholar
Scholar
4,454 Views
Registered: ‎02-27-2008
Nik,

An old, old problem (which I had more than 30 years ago designing an ASIC, too).

Long counters don't simulate well (kind of obvious, isn't it?).

Don't do it that way. Insert multiplexers to simulate a terminal count of two counts, not thousands (millions). Set the multiplexers to count to two for simulations. Set them for the proper count in the actual design for the part on the board.
Austin Lesea
Principal Engineer
Xilinx San Jose
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Highlighted
Professor
Professor
5,790 Views
Registered: ‎08-14-2007

First, simulation resolution makes very little difference in speed for modern simulators.

 

Second, as mentioned, the best way is to simulate a shorter counter.  Here's a trick

I picked up from comp.arch.fpga for automatically using smaller counts during simulation:

 

if( count=50000000

-- synthesis translate_off

 / 1000000

-- synthesis translate_on

) then
IO(0)<='1';
elsif(count=100000000

-- synthesis translate_off

 / 1000000

-- synthesis translate_on

) then

 

In this case for simulation, but not synthesis, divide the constants by 1 million.

Then when you go to synthesize you still get the longer counts and don't need

to remember to take the "simulation stuff" out of the design.

 

-- Gabor

-- Gabor

View solution in original post

Highlighted
Visitor
Visitor
4,436 Views
Registered: ‎01-17-2012

thank you very much i was not aware of that.

 

-Nik-

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