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Observer binliu
Observer
268 Views
Registered: ‎06-05-2018

how to execute the RTL simulation on the TCAM IP Core generated by the SDNet

I am student from college and meet with an obscure problem for two weeks when I want to execute the RTL simulation on the TCAM IP Core generated by the SDNet.

My computer operating system is Win10; the version of SDNet is 2018.2 and the version of Vivado is 2018.2.

My operations are as follows.

(1) write an procedure "my_tcam.sdnet" according to UG1012(ug1012-sdnet-packet-processor), and the top class is "LookupEngine(TCAM,1024,32,20,1)"

(2) compile the above file (mt_tcam.sdnet) in "cygwin64" terminal and the terminal returns that "compilation successfully"

(3) Then I create the two files "Packet.user" and "lookup.tbl" , finally run the C++ level simulation successfully.

(4) However, when I want to do the RTL level simulation by running "vivado_sim.bash"  generated by SDNet, I meet the following problems and  I don't know how to see the waveform.d18a4feaace88bd1ee30c7d10121c86.png

 

 

(5) if I use the "vivado_ sim_waveform.bash", the cygwin terminal start the vivado (it displays "strart_gui"), but I cannot still see any waveform changing.

The final result is as follows.

038f989a38a4a30849908cee428aa18.png

 

(6) In view of that, I use the modelsim and run the "qusta.bash". Unfortunately, I meet the following problem. I don't modify the files "TCAM.h/c" at all !ee49ebe5665e7ee3894d5172ec62bc5.png

 

 

  

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Observer binliu
Observer
266 Views
Registered: ‎06-05-2018

Re: how to execute the RTL simulation on the TCAM IP Core generated by the SDNet

Actually, my aim is to how to insert a rule to TCAM core through the AXI-Lite Bus, but when I use the CORE in vivado, I check the interface and find that there is no corrresponding signal to transfer the necessary data (addr[10:0], key[31:0],mask[31:0],value[19:0]).187c1f55d414d000f9205044a1de8ab.png

 

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