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Visitor
Visitor
672 Views
Registered: ‎07-10-2018

how to generate 4 MHz clock from 2 MHz clock in FPGA.

Hi,

I need to generate 4 Mhz clock from 2 MHz clock . I checked clocking wizard/MMCM/PLL , but there input clock range start from 10 MHz.

I had read about using rising and falling edge detectors but they fail to give 50% duty cycle.

can DDS(direct digital synthesizer ) convert 2MHz clock frequency into 4MHz frequency??

what are the other methods to do that??

Regards
Ankit

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Scholar
Scholar
664 Views
Registered: ‎08-01-2012

Is this really a simulation question?

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Moderator
Moderator
661 Views
Registered: ‎08-08-2017

Hi @ankitkes2 

What is the device your design targetted for ?  Please check the clock buffers having dividing capability in respective device clocking user guide

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Visitor
Visitor
642 Views
Registered: ‎07-10-2018

@pthakare 

this design is for Arty board containing Artix 7 chip. fpga part no is XC7A35TICSG324-1L. 

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Scholar
Scholar
629 Views
Registered: ‎08-07-2014

@ankitkes2,

I checked clocking wizard/MMCM/PLL , but there input clock range start from 10 MHz.

You know this.

I need to generate 4 Mhz clock from 2 MHz clock .

Then the next question would be, what is the source of this 4MHz clk?

 

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Visitor
Visitor
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Registered: ‎07-10-2018

@dpaul24 

4 MHz clock has to be generated from 2 MHz clock.

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Teacher
Teacher
612 Views
Registered: ‎07-09-2009

I did not think Arty board had a 4 MHz input clock,
To a first order, you can not make a 4 MHz clock out of a 2 MHz one

Maybe if we understood a little more of your design then we could help more.

Where does the 4 MHz clock come from ? is it made inside the FPGA ?

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Scholar
Scholar
514 Views
Registered: ‎08-07-2014

@ankitkes2,

Sorry, typo...

I meant source of 2MHz clk.

But more info on the source clock is needed to answer in a better way.

Answering your question differently, just o/p 20MHz from your MMCM/PLL and write your divide by 5 logic to get 4MHz clock. Do not generate a new clock signal, you generate clock_enable signals.

Also please do not duplicate posts.

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Scholar
Scholar
490 Views
Registered: ‎05-21-2015

@ankitkes2,

To generate a 4MHz clock from a 2MHz clock ...

  1. Your board has a 100MHz clock.  Let's use it for this example
  2. Run the 2MHz clock through a 2FF synchronizer, as you would for any incoming asynchronous logic
  3. Then make the clock an input to this logic PLL
  4. You'll want to use the 100MHz input clock as the input clock for the PLL.
  5. You'll also want to set the default phase step, i_step, to 2MHz / 100MHz * 2^PHASE_BITS, or 32'h051eb852 for PHASE_BITS=32.  (Drop the low order bits for a shorter PHASE_BITS setting.)  You can hold i_ld high for one cycle to make sure this is set properly.
  6. The PLL outputs PHASE_BITS of output phase.  Take bit PHASE_BITS-2 from that output phase
  7. This will be your 4MHz clock.

Dan

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Visitor
Visitor
430 Views
Registered: ‎07-10-2018

@drjohnsmith 

The 2 Mhz clock is generated from the input data using the clock recovery algorithm. I require one 4 MHZ clock that must be synchronize to this 2 MHz clock. If i use arty board clock to generate 4 MHz than both clock would not be synchronized. and i don't know how to synchronize/align two clocks generated from different sources.

So I thought it would be better if I can generate 4 MHz clock from my original 2 MHZ clock .

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Scholar
Scholar
417 Views
Registered: ‎08-01-2012

You can always use CDC methods to get the data into the new clock domain. Usually you would use a FIFO for this..

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Scholar
Scholar
378 Views
Registered: ‎05-21-2015

@ankitkes2,

Here's a description of how an asynchronous FIFO works, such as you might wish to use in this situation.  Using it, you should have no problems passing a data stream from a 2MHz clock domain to a 4MHz clock domain.

Dan

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Xilinx Employee
Xilinx Employee
339 Views
Registered: ‎08-13-2007

Please don't crosspost

You have another thead here:

https://forums.xilinx.com/t5/Synthesis/how-to-generate-4-MHz-clock-from-2-MHz-clock-in-FPGA/m-p/1075579

and yet 3rd duplicate thread that was already steered back to one of these.

It is difficult for others to offer you coherent advice with the same subject in multiple boards/threads. Or for others to follow later.

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