02-13-2020 02:50 AM
I need to generate 4 Mhz clock from 2 MHz clock . I checked clocking wizard/MMCM/PLL , but there input clock range start from 10 MHz.
I had read about using rising and falling edge detectors but they fail to give 50% duty cycle.
can DDS(direct digital synthesizer ) convert 2MHz clock frequency into 4MHz frequency??
what are the other methods to do that??
02-13-2020 03:05 AM
What is the device your design targetted for ? Please check the clock buffers having dividing capability in respective device clocking user guide
02-13-2020 04:18 AM
I checked clocking wizard/MMCM/PLL , but there input clock range start from 10 MHz.
You know this.
I need to generate 4 Mhz clock from 2 MHz clock .
Then the next question would be, what is the source of this 4MHz clk?
02-13-2020 04:30 AM
02-14-2020 12:22 AM - edited 02-14-2020 12:52 AM
I meant source of 2MHz clk.
But more info on the source clock is needed to answer in a better way.
Answering your question differently, just o/p 20MHz from your MMCM/PLL and write your divide by 5 logic to get 4MHz clock. Do not generate a new clock signal, you generate clock_enable signals.
Also please do not duplicate posts.
02-14-2020 03:11 AM
To generate a 4MHz clock from a 2MHz clock ...
02-16-2020 10:24 PM - edited 02-16-2020 10:27 PM
The 2 Mhz clock is generated from the input data using the clock recovery algorithm. I require one 4 MHZ clock that must be synchronize to this 2 MHz clock. If i use arty board clock to generate 4 MHz than both clock would not be synchronized. and i don't know how to synchronize/align two clocks generated from different sources.
So I thought it would be better if I can generate 4 MHz clock from my original 2 MHZ clock .
02-19-2020 07:45 AM
02-21-2020 07:37 AM
Please don't crosspost
You have another thead here:
and yet 3rd duplicate thread that was already steered back to one of these.
It is difficult for others to offer you coherent advice with the same subject in multiple boards/threads. Or for others to follow later.