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Registered: ‎04-03-2017

how to instantiate a synthesizable fifo that works with 3rd party simulation tools

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I've been relying on the Xilinx unimacro library to run simulations with ghdl and VUnit.  Vivado's xsim does not fully support vhdl 1993 and is missing some features needed to run VUnit. The unimacro library is deprecated and is not supported on ultrascale devices.

According to this thread, the XPM library only has system verilog models https://forums.xilinx.com/t5/Simulation-and-Verification/no-VHDL-simulation-models-for-XPM-s/td-p/813397 .  So, I can't use it with ghdl.  I'm looking for a workaround.

Is there any way to instantiate fifos in Vivado that the synthesis tool will understand that can also be understood by a vhdl simulator like ghdl?

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Scholar
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Registered: ‎08-01-2012

What features of VHDL 93 are missing? Are you sure you dont mean VHDL 2008?

As GHDL is VHDL only you'll be out of luck with XPM. Async FIFO will require you to use a dual top level too with their glbl.v block for a GSR reset . To add even further misery it has SVA in it, which is an extra paid for feature in most simulators. Its like Xilinx are trying to force you to use their terrible simulator.

https://forums.xilinx.com/t5/Simulation-and-Verification/Simulating-XPM-FIFO-in-ActiveHDL-Error-with-2018-2-libraries/m-p/883224

The only options are:

1. Create FIFO IPs from the FIFO generator - these still produce a VHDL simulation netlist (note: its a netlist so slooow)

2. Write your own FIFOs (I did this for a sync fifo)

We have a mixed language licence, so XPM is an option, but because we only have 1 of them, writing our own sync FIFO made sense (it has the same functionality as XPM and slightly smaller).

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Registered: ‎04-03-2017
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Scholar
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Registered: ‎08-01-2012

What features of VHDL 93 are missing? Are you sure you dont mean VHDL 2008?

As GHDL is VHDL only you'll be out of luck with XPM. Async FIFO will require you to use a dual top level too with their glbl.v block for a GSR reset . To add even further misery it has SVA in it, which is an extra paid for feature in most simulators. Its like Xilinx are trying to force you to use their terrible simulator.

https://forums.xilinx.com/t5/Simulation-and-Verification/Simulating-XPM-FIFO-in-ActiveHDL-Error-with-2018-2-libraries/m-p/883224

The only options are:

1. Create FIFO IPs from the FIFO generator - these still produce a VHDL simulation netlist (note: its a netlist so slooow)

2. Write your own FIFOs (I did this for a sync fifo)

We have a mixed language licence, so XPM is an option, but because we only have 1 of them, writing our own sync FIFO made sense (it has the same functionality as XPM and slightly smaller).

View solution in original post

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Registered: ‎04-03-2017

> What features of VHDL 93 are missing? Are you sure you dont mean VHDL 2008?

I am absolutely sure I don't mean VHDL 2008.

https://github.com/VUnit/vunit/issues/209

"XSIM didn't support custom resolved types which VUnit uses. This can be worked around but it would be easier if we didn't have to" - LarsAsplund

"There is no active work to add support for xsim. There have been some preliminary tests which shows it lacks enough VHDL support of even 93 standard to accept the VUnit code. Also it has a very sluggish startup time which would hinder fast feedback when running multiple small tests. " -Kraigher.

VUnit doesn't need VHDL 2008. I think it does need some features from VHDL 2005 that Vivado associates with VHDL 2008, but the developers on VUnit say that Vivado is also missing some features needed from the 93 standard, and I believe them.

> Write your own FIFOs (I did this for a sync fifo)

All I need is a sync fifo.

I can put a small async fifo in front of a sync fifo for the cdc, and I don't need a blockram in the small one.  I do that already because I had trouble getting the reset right on the unimacro async fifo.

I've found recommendations in several places since I posted that I write a module to infer block ram and put custom fifo logic around that.

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Scholar
Scholar
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Registered: ‎08-01-2012

Ahh yes - custom resolved types. Very little used outside of VUnit and OSVVM.

And its VHDL 2002 it uses - that will be protected types.

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Registered: ‎08-25-2017

VUnit do not use custom resolved types anymore. Another limitation in XSIM that makes VUnit integration troublesome is that you cannot configure the simulator to break on asserts with severity error. At least it used to be the case. I'm not sure if this is still the case.

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Registered: ‎04-29-2019

Xilinx should support at least all the features needed for VUnit. In my new project I use a CI pipleline for automated testing and it makes things much easier. Sigasi already integrated VUnit into Sigasi Studio.

Atm this is not possible with Vivado/Xsim and makes it useless to me.

It is very poor that I have to rely on third party tools to work with the design flow that is state of the art

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