02-21-2015 06:12 PM
I am working with memory controller (MIG) on Vivado 2013.3. Since it takes a long time to initialization step of DRAM gets over I am wondering if there is any way to save all states of simulation when this initialization gets finished and next time when I want to run this simulation I start it from that step. As you probably know, there is a system task called $save to do exactly what I explained but the problem is that it is defined just in Verilog-XL and not valid in verilog 2001. So it is also useful for me to know how to change the verilog version of Vivado and if it is supporting Verilog-XL.
thanks and I really appreciate all your prompt replies.
02-21-2015 08:06 PM
02-21-2015 09:12 PM
thanks for your quick reply.
But Verilog, itself has this support ($save) but only Veilog-XL do you know if there is any way to change the version of Verilog in Vivado? I am working on MIG which is a memory interface and it has a long time calibration at every simulation run but whatever I am changing for debug has nothing with that stage so it is very helpful for me if I can make XSIM ignore that phase. If I want to change my simulator you know, because I am using MIG which is the Xilinx IP core and I have so manything which are defined just in Xilinx simulator it is very difficult to shift to another simulator.
I really appreciate if you have any other idea
02-21-2015 10:57 PM
Unfortunately $save is not a part of Verilog proper and it is not available in any Xilinx simulator. I do not to advertise for a specific product but, say, VCS is full capable of simulating all Xilinx IP (encrypted or not, including MIG code) and has the save and restore feature. Of course it's significantly more expensive but that is what you get when you need an industrial strength simulator.