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Adventurer
Adventurer
3,270 Views
Registered: ‎06-05-2012

how to see the reg signal after synthesize

Hey guys,

 

I want to trace one datapath by chipscope in my design, but after sysnthesize, I found some of reg signals are disappear. As other peoples said, I Keep hierarchy YES, and add the constraint for the the reg signal I want to see (*keep = "TRUE"*) 

But it seems no affect. Still cann't see this signal. Could somebody give me some suggestions?

 

Wei

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2 Replies
Instructor
Instructor
3,259 Views
Registered: ‎08-14-2007

Re: how to see the reg signal after synthesize

Sometimes a signal is still in the design, but has been renamed.  Remember that in a heirarchical

design, any net that goes through a module port may have different names at each level of the

hierarchy, and at the end only one of these names remains.  For XST this is normally the name

of the reg where the signal is driven.  So let's say you have a top level module that instantiates

a lower level module like

my_lower_module mlm_inst

(

  . . .

  .d_out  (data_from_mlm)

);

 

and my_lower_module has a port defined as:

 

  output wire [7:0] d_out,

 

and within the module:

 

reg [7:0] data_within_mlm;

 

assign d_out = data_within_mlm;

 

Now you have an 8 bit bus that could be called:

 

data_from_mlm

 

mlm_inst/d_out

 

or

 

mlm_inst/data_within_mlm

 

  I think in this case you'll see the last one, but it's up to XST to decide.  So you need to

search for any of these in the ChipScope inserter.

 

-- Gabor

-- Gabor
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Xilinx Employee
Xilinx Employee
3,256 Views
Registered: ‎07-16-2008

Re: how to see the reg signal after synthesize

In the case that the concerned reg signals are unconnected (sourceless or loadless), "keep" property doesn't prevent trimming. You need to apply "S" (Save Net Flag).

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