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tchin123
Voyager
Voyager
332 Views
Registered: ‎05-14-2017

how to set design parameter in simulation

I want to reduce the simulation time for the AXI-Ethernet subsystem IP and it suggest to set the EXAMPLE_SIMULATION generic as follow:

set_property CONFIG.EXAMPLE_SIMULATION (1) [get_ips <component_name>]

How or Where do I set or type this command into? Does it goes into my VHDL file, constraint file or some simulation setting in Vivado.

As for the parameter <component_name> is this the test bench or the top module name?

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dpaul24
Scholar
Scholar
323 Views
Registered: ‎08-07-2014

@tchin123 ,

You run the command in the Tcl Console window of Vivado.

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tchin123
Voyager
Voyager
278 Views
Registered: ‎05-14-2017

OK, that would help.

Is there a way to set this up without typing this long command every time Vivado is open for simulation ?

Can this be set in the Vivado GUI Setting or enter into the constraint file?

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olupj
Explorer
Explorer
228 Views
Registered: ‎01-27-2008

Hi@tchin123 

Not quite a constraint file but I use it in my build script (TCL script setting up the system) for synth, sim or both.

This becomes a setting (in the GUI) under General -> Language Options -> Generics/Parameters

set_property generic { REPO_PATH=/home/local/users/yourname/work/project/design_root } [current_fileset]

 

So once you figure it out, this technique becomes very useful to drive top level parameters / generics.

Have fun,

Jerry

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