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seban90
Visitor
Visitor
666 Views
Registered: ‎10-17-2019

how to test MIG core in VCS

I generated mig core in vivado 19.1.3 and made simple testbench with ddr4 model (simulation model from micron website).

simulation runs in vivado, but it cannot run in vcs because of segmentation fault.

Is there what I missed?

 

 

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yangc
Xilinx Employee
Xilinx Employee
625 Views
Registered: ‎02-27-2019

How do you simulate in VCS? You can refer to https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug900-vivado-logic-simulation.pdf#page=38

And compile the libraries first if you use a third-party simulator.

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seban90
Visitor
Visitor
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Registered: ‎10-17-2019

Thank you for your response.

 

My simulation target is huge size of asic system which I modified to fit it in fpga.

In my understanding, mig or other related secure ip can be compiled by vcs (as standalone compilation environment) even if all are encrypted.

also, I listed all required files to compile them by vcs and vlogan was able to compile all.

 

this is my option

In Makefile,

VLOGAN = vlogan

VCS = vcs

 

VLOGAN_OPT +=  -full64

VLOGAN_OPT +=  -l vlogan.sim.log

VLOGAN_OPT +=  -work work

VLOGAN_OPT +=  -timescale=1ns/1ps

VLOGAN_OPT +=  -error=noMPD

VLOGAN_OPT +=  +v2k

VLOGAN_OPT +=  +libext+.v

VLOGAN_OPT +=  +define+ALL_DEFINES_FOR_FPGA

VLOGAN_OPT +=  +systemverilogext+.sv

VLOGAN_OPT +=  +systemverilogext+.svp

VLOGAN_OPT +=  +systemverilogext+.svh

VLOGAN_OPT +=  -assert svaext

VLOGAN_OPT +=  -f sim_file_lists.f

 

VELAB_TOP += -full64

VELAB_TOP += debug_access+all

VELAB_TOP += -deraceclockdata

VELAB_TOP += -top glbl

VELAB_TOP += -top testbench

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