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3,087 Views
Registered: ‎03-16-2015

how to write content of the BRAM to text file?

 how to write content of the BRAM to text file? What is the problem with following test bench?

 

module mem1_tb;

// Inputs
reg clka;
reg [17:0] addra;
reg [7:0] dina;

// Outputs
wire [7:0] douta;
integer f,i;
// Instantiate the Unit Under Test (UUT)
mem1 uut (
.clka(clka),
.addra(addra),
.dina(dina),
.douta(douta)
);

initial begin
// Initialize Inputs
clka = 0;
addra = 0;
dina = 0;

// Wait 100 ns for global reset to finish
#100;

#2;

end


always #5 clka = ~clka;


always #6 addra = addra +1'b1;

initial
begin
f = $fopen("output.txt","w");
end


always @(posedge clka) begin
$fwrite(f,"%d\n",douta);
end

endmodule

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2 Replies
thakurr
Moderator
Moderator
3,034 Views
Registered: ‎09-15-2016

Hi subimanc@gmail.com

 

To my understanding as both initial and always statements execute at 0 ns, hence there is no guarantee that the file will be opened before you write to it.

Also you forgot to close the file with $fclose(f).

Check the below arctile, hope it helps:

https://stackoverflow.com/questions/25607124/test-bench-for-writing-verilog-output-to-a-text-file

 

Regards

Rohit

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Regards
Rohit
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dgisselq
Scholar
Scholar
3,025 Views
Registered: ‎05-21-2015

If your memory sits on a wishbone bus within an FPGA (or Verilator simulation), then you might find this project (https://github.com/ZipCPU/dbgbus) to be valuable.  Not only does the demonstration show how to read/write an FPGA block RAM from an external (PC) host, but there's also a scope within it allowing you to "see" what's going on within your hardware.  See this page for more details.

 

Dan

 

P.S.  There is a lot more that could be said and shared here, but for some reason I'm getting an error that says I'm trying to comment on a "read-only" forum.

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