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Adventurer
Adventurer
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Registered: ‎01-02-2012

hwcosim HIL for Zynq

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Dear all,

 

I am trying to do a Hardware-in-the-loop (HIL) Simulation for a simple Zynq-based Embedded design.

 

I have written a simple testbench for my embedded design, and a tcl script with the required commands (restart, scope [target], hwcosim [sharedCable: TRUE], run 0ns). I have also set the additional Fuse options for ISim (-hwcosim_instance, -hwcosim_clock, -hwcosim_board, -hil_zynq_ps). That should be it for the Simulation Part (afterwards one is required to correctly set up the PS within SDK, etc.). OK so far, ISim launches and downloads the bitstream. And then, all out of a sudden, I get an error message stating "could not find the HwCosim handle for current scope", and the simulation is terminated (the generated .exe file crashes).

 

Unfortunately I was unable to find any information on that specific error message. Does anyone happen to know anything about it?

 

Thanks in advance and kind regards,

David

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Adventurer
Adventurer
11,989 Views
Registered: ‎01-02-2012

Hi unmangp,

 

thanks for your reply! Well, I finally got it working, although I DID NOT USE those commands at all. Apparently the additional Fuse Options for compilation are enough - after that I simply run the Simulator!

 

Attention is to be paid when handling the ISim and SDK during Co-Simulation; it seems that the specific sequence of actions is of great significance for the tools NOT to crash. Specifically:

 

1) After starting ISim, DO NOT run the simulation.

2) Export your design to SDK, and start DEBUGGING your application.

3) Now you may run the simulation in ISim.

4) If you want to pause it, you first have to PAUSE ISim. Then you may stop debugging your app and change whatever you want to change - BUT you need to TERMINATE and REMOVE the instance!!!

5) Finally, you repeat steps 2 & 3: you first start debugging, and THEN re-run ISim.

 

Cheers,

David

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-07-2012

 

Can you make sure that in the TCL script, the scope command captures the design heirarchy to the PS correctly ? 

 

I think the error message is occuring during the scope command. 

 

You can also try giving the commands one by one in the ISIM command prompt and you wil find out which command is giving this error.

 

Then, I might be able to help you in a better way. 

 

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Adventurer
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Registered: ‎01-02-2012

Hi unmangp,

 

thanks for your reply! Well, I finally got it working, although I DID NOT USE those commands at all. Apparently the additional Fuse Options for compilation are enough - after that I simply run the Simulator!

 

Attention is to be paid when handling the ISim and SDK during Co-Simulation; it seems that the specific sequence of actions is of great significance for the tools NOT to crash. Specifically:

 

1) After starting ISim, DO NOT run the simulation.

2) Export your design to SDK, and start DEBUGGING your application.

3) Now you may run the simulation in ISim.

4) If you want to pause it, you first have to PAUSE ISim. Then you may stop debugging your app and change whatever you want to change - BUT you need to TERMINATE and REMOVE the instance!!!

5) Finally, you repeat steps 2 & 3: you first start debugging, and THEN re-run ISim.

 

Cheers,

David

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Visitor
Visitor
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Registered: ‎10-18-2012

Dear all;

 

I am also trying to do a Hardware-in-the-loop (HIL) Simulation for a simple Zynq-based Embedded design.

I performed the steps that dfuschelberger mentioned. I have also watched the steps in the document "xapp 744 HIL Simulation for the Zynq-7000".

 

However the problem is; the processors stays on the code (line) that it communicates with the PL part througt the axi interconnect. ie. the code that sets the direction of the gpio's

 

Do you have any idea about this problem.

 

All replies are appreciated.

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Adventurer
Adventurer
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Registered: ‎01-02-2012

Hi,

 

sounds like the processor's not getting the appropriate response from the Interconnect and gets stalled. Are you using Xilinx AXI Interconnect IP within your fabric? If you mentioned some more details about your setup I'd probably be able to help you out.

 

BR,

David

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Visitor
Visitor
9,429 Views
Registered: ‎10-18-2012

Hi and thanks for your attention.

 

I watch the following steps;

1) Open Plan Ahead 14.3. Open new project for ZC702 development board, Add an Embedded source. add the led peripheral.(together with the axi interconnect bus)

2) Remove the Fclk0 connection of the processor (which drives the clock of the axi interconnect) and make it external.

3) Make the reset pin of the axi bus external. Generate netlist and exit xps.

4) Return planahead and generate top vhd source.

6) Add a testbench and write the testbench code which just clicks the axi clk and set the axi reset.

7) Click Run Behavioral Simulation > Options. Adjust more fuse opotions as in xapp 744.

8) connect the uart and jteg cables, power on the device. Launch simulation. And wait until the bitstream is downloaded successfully.

9) return to the planahead and export hardware to sdk. create a new hello world c code. Write the codes just blinks the leds. (The codes are tested by implementing on the device the aim is learn about HIL)

10) debug as and wait at the beginning of the code.

11) Run simulation and run the debug session.

 

Observed problem:  The processors writes the uart comments before the PL related codes but do not writes the uart comments after that. Which means it is not getting the appropriate response from the Interconnect and gets stalled as you mentioned. I do not see any appropriate think in the simulation console. I need help for this part

 

Another question: is the clock of the processor driven by the simulation? if it is how? Does the more fuse options part do that? Because we don't touch that.

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Adventurer
Adventurer
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Registered: ‎01-02-2012

Hi sacoskun,

 

your flow is correct, that's exactly how I was doing it.

 

Funny thing, while going through the updated document I noticed that they now mention all the stuff I came up with back then in the WebCase that I'd opened. :-) One part of it is following (which I'd tell you anyway):

 

Avoid Single Stepping in The Software
For sections of the program that do not generate an AXI transaction, single stepping the 
software should be fine. But, a cable locking error might occur if trying to single step (step in or 
Step over) over sections of code that generate AXI transactions. Instead of single stepping, try 
to place break-points and then resume debugging the software from that point on.

 

So basically, DON'T step-through your SW, do a single run. Hope this helps.

 

Furthermore, regarding the PS clock: it's a free-running clock (basically, it's the PS_CLK reference oscillator on the board in combination with the internal SW PLL, which generates all the clock signals needed within the PS).

 

BR,

David

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Visitor
Visitor
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Registered: ‎10-18-2012
Hi dfuschelberger
I tried adding break points and resuming the debug. However it does not worked. Then I set up the same hardware as in the zynq_hil_timer tutorial project. Although the ready tutorial project was working, the new design which was generated by doing the same things in the tutorua doc. did not work. The only difference that I recognize was the version of the system7_0. In the tutorial project it was 4.00.a and it is 4.02.a in mine. Do you think could that be the reason? The problem is again the same. The c code debug collapse when the line of interconnection is reached. I guess the isim setup reason the problem.

Any reponses and helps are appreciated.
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Adventurer
Adventurer
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Registered: ‎01-02-2012

Do you get any error messages in either SDK or ISIM? If so, please post them. If not, please post your C code. I doubt that the version of PS7 has anything to do with it.

 

What JTAG cable are you using?

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Visitor
Visitor
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Registered: ‎10-18-2012
I handle the problem. It was related with the axi bus. I double clicked on the axi intetconnect and changed the following properties.
1. Under the general tab turn off the "check for transaction error" initially it was automatic.
2. Under the "master-slave specific setting" on the tab "slave register slices" turn the "read address" and "write adress" to "fully registered". It was initially "bypass"

Now, i am able to do hardware in the loop. The bad think is i could not find anything about this issue in any document. :(

Lastly, Thank you very much for your kind responses.
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Adventurer
Adventurer
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Registered: ‎01-02-2012

Well, that's because it's not really an "issue"; it's more likely called "reading the datasheet"... :-)

 

Anyway, I'm glad that you achieved running HIL. Be aware that this feature isn't mature yet at all, and that you'll most probably run into several additional issues while experimenting with it.

 

Good luck!

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Visitor
Visitor
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Registered: ‎10-18-2012

Hi again dfuschelberger

 

The process of communication between the Isim and the PS through JTAG is a black box for me.

  1)  What kind of a bitstream is downloaded to the device by Isim before running the simulation. What does this bitstream exactly do to build communication through JTAG ?  It is called as precompiled bitstream and does it the same file for every project?

  2) Does the communication occurs for every axi bus clock? ie. is the bus connection between the axi bus and the PS transfered through the JTAG for every clock?

  3) What about more fuse options? The xapp 744 saw the details about this option beyond the scope of the document.I just know that Isim uses this comments for compilation.

  4) Lastly, the processors runs much more quickly for the parts that is not related with the axi bus (ex: DDR operations), and slows down for the axi buses. Is this knowledge that I got by reading between the lines is correct?

 

What I need is a document that makes me clear about these questions? Can you recommend any such except xapp 744?  :)

 

Thanks.

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Adventurer
Adventurer
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Registered: ‎01-02-2012

Hi,

 

1) Although I do know the principles of a JTAG chain, I'm not aware of details regarding our setup over here, so I won't answer you. Nevertheless, this shouldn't bother you.

 

2) Your PL design, and therefore the AXI port which you connect to, is clocked by the Test Bench clock that you provide it with. Yes, the simulated portion is definitely written for every clock cycle.

 

3) Well, HIL for Zynq isn't the only HW Co-simulation. Just make yourself comfortable with HW CoSim in general. Xapp_744 exclusively addresses Zynq HIL.

 

4) The PS has several clock domains. The AXI ports are connected to one of those through an Asynchronous clock domain bridge. This is common. Furthermore, don't forget that the PS is ALSO using AXI. (Take a look at the TRM, UG585, p.59 : http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)

 

Unfortunately, I'm not aware of such a document - and I doubt that you'll ever find such an overview-doc within Xilinx, at all.

 

Best,

David

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Visitor
Visitor
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Registered: ‎12-08-2009

Hello

 

I am trying to run the timer_single_clock example from xapp744. I can start up the simulator and the bitstream is downloaded successfully. But then in the SDK debugger I see that the program hangs in boot.S at the following loop:

 

205  /* poll for completion */

206  Sync: ldr r1, [r0]

207  cmp r1, #0

208  bne Sync

 

and thus never reaches the main() function.

 

Can anybody help me with that?

 

Thanks a lot,

Juergen

 

 

 

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Visitor
Visitor
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Registered: ‎12-08-2009

Hi all

 

Issue is resolved. I used the wrong setting for SW16. All switches need to be in the right position (JTAG mode) for HIL to work. 

 

Regards,

Juergen

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Adventurer
Adventurer
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Registered: ‎10-24-2007

Hi,

 

I am trying to get HIL example working on the zynq zedboard. At the point of axi transaction, processor waits forever and ISIM also doesn't show any activity on the AXI channels.

 

These are the steps I followed.

1. Added the following code the hwcosim.bsp

'zed-jtag' => { 
'Description' => 'ZC702 (JTAG)',
'Vendor' => 'Xilinx',
'Type' => 'jtag',
'Part' => 'xc7z020-1clg484',
'Clock' => [
{
'Period' => 10,
'Pin' => 'Y9',
},
],
'BoundaryScanPosition' => 1,
},

1. Created a new plan ahead project and a sub xps project targeting the zynq zedboard with a timer peripheral.

2. In xps, removed Fclk0 connection and made clk and reset pin of the axi bus external.

Added the following lines the MHS(attached) for the timer

PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1

and AXI interconnect

PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
PARAMETER C_RANGE_CHECK = 0

3. Back in plan-ahead, created the top module and added the test bench too generate the clk and reset.

4. Under behavioral simulation fuse options, added the following 

hwcosim_instance /testbench/dut/module_1_i/processing_system7_0 -hwcosim_clock M_AXI_GP0_ACLK -hwcosim_board zed-jtag -hil_zynq_ps

5. Powered the board. Ran behavioral simulation. It managed to successfully download the bit stream.

6. Export and launch SDK and ran in debug mode.

7. Enabled simulation run all

8. In SDK, ran both resume and step mode.

9 . Terminal programs shows "Configuring the timer as an up-counter"  and get hung.

 

Is there a step missing here?

Log file shows bit stream is successfully download to the FPGA.

Diff (attached) of my spec with the reference spec file for given HIL example on ZC702 shows only relevant logical changes.

My setup is Xilinx 14.4 on ubuntu.

 

How does the axi channles get tunneled through JTAG from the ARM to the ISIM application? Is there a way to verify it in XMD? 

 

 

 

 

 




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Adventurer
Adventurer
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Registered: ‎01-02-2012

Hi,

 

by the time I was using HIL, Avnet's official statement was that "HIL is not yet available on ZedBoard, and that it is not planned to be supported before Q1 2013. Check it out: http://zedboard.org/content/zynq-hil-co-simulation-zedboard

 

Cheers,

David

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Adventurer
Adventurer
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Registered: ‎10-24-2007

Hi David,

 

Thanks for the link. I posted there as well and there is no update yet from avnet. The reply from xilinx webcase suggested there is no logical reason it shouldn't work on the zedboard though not officially supported.:-)

The changes in the bsp should be enough, since zynq is supported. Is there any logfile or anyway to verify that AXI channels are being tunned through JTAG to ISIM and back?

 

I have big system on chip design to debug and the alternative option is use chipscope or BFM(need an extra license). :(

 

Cheers,

Shakith

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Adventurer
Adventurer
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Registered: ‎01-02-2012

Hi Shakith,

 

well, when I had opened a WebCase back then, Xilinx' reply was that it would require a "specific bitstream" (!), which was not available at that time. Later on, Avnet came along with the bsp for ZedBoard and, apparently (now that I actually read your post..), with other options regarding HIL support on ZedBoard. I couldn't even download the bitstream back then. Anyway, according to the procedure you describe, I'd say that it really should work, one way or another. Out of experience, when the processor gets hung, it usually has to do with the AXI communication itself. Are you using Xilinx AXI Interconnect or some custom IP?

 

However, I'd suggest you go with the Chipscope option anyway - HIL seemed and seems to me as an unreliable debugging method (even though much promising). One more thing: use the classic ILA core, not the AXI Chipscope IP. :-)

 

Good luck and kind regards,

David

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Adventurer
Adventurer
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Registered: ‎10-24-2007

Thanks.

 

I am just using Axi_timer connected with AXI LITE interconnect.

 

I decided to move to chipscope for now. 

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Registered: ‎04-17-2013
any news? I have the exact same problem of cyberdevinda
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