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679 Views
Registered: ‎10-28-2019

i got different simulation result compare on different computer

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this is my friend code test on basys3 machine about 4-bit lfsr. the rar file is my code

Debounce https://www.digikey.com/eewiki/download/attachments/13599139/DeBounce_v.v?version=1&modificationDate=1365097105920&api=v2

source code

`timescale 1ns / 1ps

module Ex1(sr,pb,load,x0,clk);

    input clk;

    input pb;

    input [3:0] x0;

    input load;

   

    output reg [3:0] sr;

    wire x;

    reg reset=1;

    wire pb_out;

    DeBounce_v db (clk,reset,pb,pb_out);

    assign x=sr[3]^sr[2];

    //always @(posedge clk)

    always @(posedge pb_out)

    begin

    if (load)

        sr={sr[2:0],x0};

    else

        sr={sr[2:0],x};

        end

endmodule

 

TestBench:

 

`timescale 1ns / 1ps

module Test_Ex1(

);

reg clk;

reg pb;

reg [3:0] x0;

reg load;

wire [3:0] sr;

Ex1 uut(

.clk(clk),

.pb(pb),

.x0(x0),

.load(load),

.sr(sr)

);

initial begin

clk=0;

x0=4'b0101;

load=1'b0;

#100;

load=1'b1;

x0=4'b0101;

#100;

load=1'b0;

x0=4'b0101;

#100;

load=1'b1;

x0=4'b0101;

#100;

load=1'b0;

x0=4'b0101;

#100;

load=1'b1;

x0=4'b0101;

#100;

load=1'b0;

x0=4'b0101;

#100;

load=1'b1;

x0=4'b0101;

#100;

load=1'b0;

x0=4'b0101;

end

 

initial begin

forever begin

#30;

clk=!clk;

end

end

endmodule

myfriend.pngthis is from my friend

me.pngmy simulation,

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1 Solution

Accepted Solutions
dror_m
Observer
Observer
644 Views
Registered: ‎06-19-2019
input [3:0] x0;
output reg [3:0] sr;
sr={sr[2:0],x0};
first of all u r pushing 7 bits to 4 bits
the difference in simulation: in one u put sr and in the other SR (capital letters), Verilog is case sensitive

View solution in original post

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4 Replies
dror_m
Observer
Observer
645 Views
Registered: ‎06-19-2019
input [3:0] x0;
output reg [3:0] sr;
sr={sr[2:0],x0};
first of all u r pushing 7 bits to 4 bits
the difference in simulation: in one u put sr and in the other SR (capital letters), Verilog is case sensitive

View solution in original post

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637 Views
Registered: ‎10-28-2019

1)about this one input [3:0] x0;

i already fixed i my code.

2) about SR and sr, i think they are not the big problem. Since even if i put those are the same character they doesnt work on my machine

And as far as i concernred .sr(SR) this one also work, cause i already write a lot of different code in other labs and i write different input in source code like C and simulation CLK and in simulation code i write for example lfsr uut( . C(CLK)) it still accepts my code and run the simulation perflectly fine

by the way do you have the simulation output like my friend, if you answer yes i will modify my code gain

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graces
Moderator
Moderator
555 Views
Registered: ‎07-16-2008

I could not reproduce the first simulation waveform. As I see it, pb_out remains X and doesn't trigger the sr toggling.

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546 Views
Registered: ‎10-28-2019

my friend's simulation output also looks like that, what i want is to let the [3:0] sr to have the output like my friend. 
i think it must because that my machine dont have Basys 3 on the board then i have to use XC7A35T-1CPG236C as Basys3, my friend just acc essBasys3 on his project device but i dont have it. THis trivia different project part may lead to this problem. 

that pb_out displays X is acceptable

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