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Observer bondylep
Observer
1,021 Views
Registered: ‎10-09-2018

ies simulate with vhdl err

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Hi,

 

i use ies simulate with my project ,there is error show dependent checksum module fifo_generator_v13_1_4.fifo_generator_v13_1_4:module(VST) does't match with the checksum that's in the header of : LIB_FIFO_V1_0_8.SYNC_FIFO_FG:IMPLEMENTION(AST).

 I use vivado 2017.2, IES is 14.2.

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Observer bondylep
Observer
954 Views
Registered: ‎10-09-2018

Re: ies simulate with vhdl err

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I have solved the problem. my project is originated start in vivado 2015, i updated the project to 2017 in windows then copy to linux to simulate. so occur error.

Now I updated it in linux, then no problem.

 

 thank you anyway!

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Xilinx Employee
Xilinx Employee
999 Views
Registered: ‎07-16-2008

回复: ies simulate with vhdl err

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Did you pre-compile the simulation libraries successfully with compile_simlib? 

BTW, the compatible IES version for Vivado 2017.2 is 15.20.014.

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Observer bondylep
Observer
988 Views
Registered: ‎10-09-2018

回复: ies simulate with vhdl err

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i precompiled the library with one err with smart_connect IP, but i doesn't use this, this may be ies version problem, but for my err, i don't think it is the version problem.

I have setup the project in windows vivado, then copy it to linux to simulate. both system is vivado 2017.2 ,is it the problem?

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Moderator
Moderator
979 Views
Registered: ‎09-15-2016

回复: ies simulate with vhdl err

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Hi @bondylep,

 

Can you please try compiling simulation libraries with supported version of IES 15.20.014 with Vivado 2017.2. Then try simulating your design using these libraries and check if you still come across this error. Please let us know the outcome of it.

 

Thanks & Regards,

Sravanthi B

Thanks & Regards,
Sravanthi B
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Observer bondylep
Observer
971 Views
Registered: ‎10-09-2018

回复: ies simulate with vhdl err

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it have some trouble to changing ies to 15.2, I change to vivado to simulate ,it alse have err showing ERROR: [VRFC 10-113] /opt/Xilinx/Vivado/2017.2/data/xsim/ip/cmpy_v6_0_12/cmpy_v6_0_12.vdbl needs to be re-saved since xbip_utils_v3_0_7.xbip_utils_v3_0_7_pkg changed.

I also simulat alone with the error IP, it is OK, so I think the error have nothting to do with the IES version.

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Observer bondylep
Observer
967 Views
Registered: ‎10-09-2018

Re: ies simulate with vhdl err

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the same project in windows vivado simulation is ok, but nok in linux vivado, and display the above error

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Observer bondylep
Observer
955 Views
Registered: ‎10-09-2018

Re: ies simulate with vhdl err

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I have solved the problem. my project is originated start in vivado 2015, i updated the project to 2017 in windows then copy to linux to simulate. so occur error.

Now I updated it in linux, then no problem.

 

 thank you anyway!

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Moderator
Moderator
949 Views
Registered: ‎09-15-2016

Re: ies simulate with vhdl err

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Hi @bondylep,

 

I am glad to know that the issue got resolved. Can you please close this thread by marking your post with solution as accepted solution.

 

Thanks & Regards,

Sravanthi B

Thanks & Regards,
Sravanthi B
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