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phara0h
Observer
Observer
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Registered: ‎12-17-2017

include files in SystemVerilog

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usually I use the compiler directive

`include "filename.ext";

to include files, but recently I've seen the syntax

include filename.ext;

in a SystemVerilog file. This syntax seems to work only in $unit, at least with Vivado 2020.2. Is this standard SystemVerilog? I haven't found any reference in LRM 3.1.a or anywhere on the net.

 

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miti
Xilinx Employee
Xilinx Employee
242 Views
Registered: ‎06-10-2020

@phara0h

Both of the include statements are valid as per LRM. Please refer LRM 1800-2017 section 22.4 and 33.3.2 respectively for mentioned syntax.

Regards,

Miti

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miti
Xilinx Employee
Xilinx Employee
243 Views
Registered: ‎06-10-2020

@phara0h

Both of the include statements are valid as per LRM. Please refer LRM 1800-2017 section 22.4 and 33.3.2 respectively for mentioned syntax.

Regards,

Miti

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phara0h
Observer
Observer
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Registered: ‎12-17-2017

Ah, now I inderstand why "include filename.ext;" is not valid inside a module. Thanks.

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