include files in SystemVerilog

[phara0h]

usually I use the compiler directive

`include "filename.ext";

to include files, but recently I've seen the syntax

include filename.ext;

in a SystemVerilog file. This syntax seems to work only in $unit, at least with Vivado 2020.2. Is this standard SystemVerilog? I haven't found any reference in LRM 3.1.a or anywhere on the net.

[miti · Accepted solution]

@phara0h; 

Both of the include statements are valid as per LRM. Please refer LRM 1800-2017 section 22.4 and 33.3.2 respectively for mentioned syntax.

Regards,

Miti

[phara0h]

Ah, now I inderstand why "include filename.ext;" is not valid inside a module. Thanks.