01-28-2021 02:27 PM
Hi,
i'm trying to practice myself with AXI and DDR2.
i've created an example design for MIG that works well.
i took control over the "axi4_tg" to manage by myself the writes and reads.
i believe i followed the rules of the AMBA AXI, including the byte-invariant (although my burst is only 1), but yet the reads are incorrect.
http://www.gstitt.ece.ufl.edu/courses/fall15/eel4720_5721/labs/refs/AXI4_specification.pdf
what could be the reason for the mistake?
please see pictures attached.
thank you,
Oryan.
01-29-2021 12:46 PM
problem solved.
because my AXI is 32b, i had to increment the address by 4 instead of 1.