cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
oryan_ye
Visitor
Visitor
288 Views
Registered: ‎09-25-2016

incorrect read from DDR simulation

Hi,
i'm trying to practice myself with AXI and DDR2.
i've created an example design for MIG that works well.
i took control over the "axi4_tg" to manage by myself the writes and reads.
i believe i followed the rules of the AMBA AXI, including the byte-invariant (although my burst is only 1), but yet the reads are incorrect.
http://www.gstitt.ece.ufl.edu/courses/fall15/eel4720_5721/labs/refs/AXI4_specification.pdf

what could be the reason for the mistake?
please see pictures attached.

thank you,
Oryan.

 

Tags (2)
AXI read from DDR wstrb.PNG
AXI write to DDR wstrb.PNG
0 Kudos
1 Reply
oryan_ye
Visitor
Visitor
229 Views
Registered: ‎09-25-2016

problem solved.
because my AXI is 32b, i had to increment the address by 4 instead of 1.

0 Kudos