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Explorer
Explorer
4,275 Views
Registered: ‎12-21-2009

independent clock FIFO

Hi all

 

I have generated an asynchronous FIFO using the core generator, set the write clock to 125MHz and read clock to 50Mhz then i statrted to simulate the generated memory using modelsim. First i assert the reset input and then deasset it, set the din value and assert the wr_en and write some words then i deassert the wr_en, the problem is that the empty flag remains high and valid remains zero which means i can not read from the FIFO altough i have writen some words.

 

Any help ?

Thanks in advance

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2 Replies
Instructor
Instructor
4,272 Views
Registered: ‎08-14-2007

Re: independent clock FIFO

One of the most common problems with simulating Xilinx IP including cores

and primitives, is forgetting to wait 100 ns after simulation starts to account

for global set & reset (GSR).  Another one that pops up in Verilog, but is

related to this issue, is to forget to assign a `timescale directive to the

test bench.  I think the default for ModelSim is either picoseconds or

femtoseconds, so if you have #100 to wait for end of GSR you're not

really waiting 100 nanoseconds, but 100 of whatever ModelSim defaults

the time scale to.  If you can see from your waveform that you have

waited at least 100 ns before releasing rst and asserting wr_en,

then maybe you can post a waveform to show what's happening.

 

-- Gabor

-- Gabor
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Observer mroberto
Observer
3,879 Views
Registered: ‎08-09-2012

Re: independent clock FIFO

Also, you need to wait for the signal FULL to go low, check this post:

 

 

http://forums.xilinx.com/t5/Simulation-and-Verification/LogiCORE-IP-FIFO-Generator-v9-1/m-p/272814

 

Regards,

Marcelo.

 

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