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qweqwe077
Observer
Observer
612 Views
Registered: ‎08-28-2008

isim do not work with `default_nettype directive

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Hello. I am using ISE14.7. I have my verilog module with directive `default_nettype. And I can synthesize module. When I try to run isim - it return error :

FATAL_ERROR:Simulator:CompilerAssert.h:40:1.29 - Internal Compiler Error in file ../src/VlogDecl.cpp at line 1483 For technical support on this issue, please visit http://www.xilinx.com/support.

 

If I comment directive `default_nettype - all work fine. How can I run simulate with this directive? How can I know in verilog file, if we run simulation or not? (then, I can use `ifndef directive to on/off directive `default_nettype). Or, may be there are any more variants to do this? (The way to use `define - to comment and uncomment when I do simulate or synthesize  - doesn`t suit me.)

Thanks.

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graces
Moderator
Moderator
568 Views
Registered: ‎07-16-2008

You may want to try XILINX_ISIM macro to control whether or not ISIM is used in the design flow. It is a Verilog predefined-macro. The value of this macro is 1. 

Example:

module
isim_predefined_macro;
integer fp;
initial
begin
`ifdef XILINX_ISIM
$display("XILINX_ISIM defined");
fp = $fopen("ISIM.dat");
`else
$display("XILINX_ISIM not defined");
fp = $fopen("other.dat");
`endif
$fdisplay (fp, "results");
end
endmodule

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graces
Moderator
Moderator
569 Views
Registered: ‎07-16-2008

You may want to try XILINX_ISIM macro to control whether or not ISIM is used in the design flow. It is a Verilog predefined-macro. The value of this macro is 1. 

Example:

module
isim_predefined_macro;
integer fp;
initial
begin
`ifdef XILINX_ISIM
$display("XILINX_ISIM defined");
fp = $fopen("ISIM.dat");
`else
$display("XILINX_ISIM not defined");
fp = $fopen("other.dat");
`endif
$fdisplay (fp, "results");
end
endmodule

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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