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210 Views
Registered: ‎03-08-2019

issue implementing xapp524 ISERDES2 in MSB first DDR 2 wire bytewise for ADC

Hello,

I'm currently implementing a LVDS interface for ADC using ISERDES2.

I have based my development on the XAPP524 and its associated design but I'm facing an issue during bit alignement.

I'm in 2 wire mode, DDR, bytewise and MSB first.

I have try some modification on design but I'm bloked.

Patern F0F0 is found but even bits arrive 1 clockdiv before odd bits.

I have used a ramp an data to put in evidence this fact.

double nibble is for 16bits 1 wires so is not activated, and I'm not sure it is the problem.

what should I do to make my design working?

Best regards

Christian 

 

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148 Views
Registered: ‎03-08-2019

Re: issue implementing xapp524 ISERDES2 in MSB first DDR 2 wire bytewise for ADC

depending the use frequency iserdes "_p" and iserdes "_n" doesn't start on the same clk_div after CE1.
serdes on inverted clock start with 1 clkdiv delay compare to other serdes.
anyone have an idea to correct that issue?
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