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Visitor
Visitor
20,273 Views
Registered: ‎03-14-2016

<packagename> is not compiled in library xil_defaultlib

Hi,

 

I am having a problem in Vivado whereby a package which I have written shows up as not compiled at simulation time. The error messages are:

 

 

INFO: [VRFC 10-163] Analyzing VHDL file "/home/simonra/vhdl/rfc4175Packetiser/source/test/tb_rfc4175inserter.vhd" into library xil_defaultlib
ERROR: [VRFC 10-149] 'video_types' is not compiled in library xil_defaultlib [/home/simonra/vhdl/rfc4175Packetiser/source/test/tb_rfc4175inserter.vhd:5]
INFO: [VRFC 10-307] analyzing entity tb_rfc4175inserter
ERROR: [VRFC 10-1504] unit tb_rfc4175inserter ignored due to previous errors [/home/simonra/vhdl/rfc4175Packetiser/source/test/tb_rfc4175inserter.vhd:7]

 

 

The package does not indicate any syntax errors, and is a simple utility package for containing some types:

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package VIDEO_TYPES is

  subtype sdiPipelineElement is STD_LOGIC_VECTOR(63 downto 0);
  subtype hvfPipelineElement is STD_LOGIC_VECTOR(2 downto 0);
  type sdiPipelineType is array (integer range <> ) of sdiPipelineElement;
  type hvfPipelineType is array (integer range <> ) of hvfPipelineElement;

end package VIDEO_TYPES;

package body VIDEO_TYPES is

end package body VIDEO_TYPES;

 

 

My test bench using this library (tb_rfc4175packetiser.vhd) has the following declarations at the top:

 

 

library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VIDEO_TYPES.ALL;

The package file shows up at the top of the compile order list for simulation.

 

Things I have tried:

 

About my system:

  • OS Ubuntu 14.04 LTS
  • Vivado 2015.4

 

Any help much appreciated.

 

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22 Replies
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Xilinx Employee
Xilinx Employee
20,257 Views
Registered: ‎09-13-2014

Re: <packagename> is not compiled in library xil_defaultlib

Two things to notice

 

1> ERROR message

ERROR: [VRFC 10-149] 'video_types' is not compiled in library xil_defaultlib

 

2> Use model 

use work.VIDEO_TYPES.ALL;

 

Which means that the test bench has been compiled in library 'xil_defaultlib'. Make sure that

 

1> You are adding your package in project

2> Library to this package is set to 'xil_defaultlib'

 

--dhiRAj

aa

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Visitor
Visitor
20,251 Views
Registered: ‎03-14-2016

Re: <packagename> is not compiled in library xil_defaultlib

Hi,

 

Thanks for your help on this. I attach an image of the libraries tab in vivado.

 

vivado.png

 

This suggests to me that the package (video_types.vhd) is in xil_defaultlib and also included in the project.

 

When I try to add the file to the project again to be sure I get:

 

WARNING: [filemgmt 56-12] File '/home/simonra/vhdl/rfc4175Packetiser/source/implementation/video_types.vhd' cannot be added to the project because it already exists in the project, skipping this file

Which again suggests that Vivado is happy that this file exists within the porject.

 

I've checked the source file properties for video_types.vhd and it shows library as xil_defaultlib as expected:

 

vivado2.png

 

Thanks again for your help.

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Xilinx Employee
Xilinx Employee
20,246 Views
Registered: ‎08-01-2008

Re: <packagename> is not compiled in library xil_defaultlib

This is a known issue when using package files in VHDL and trying to use the settings within your testbench for "Post Synthesis Functionl/Timing Simulation".

The package file is not being included in the project file (.prj) generated for simulation compilation.

It is only included for implementation in the GUI even though they are added as both simulation and implementation sources.

To work around the issue:

  1. Avoid using constants etc defined in the package file in your testbenches when simulating "Post Synthesis" or "Post Implementation" design.
     
  2. The other option is to generate the simulation scripts only by selecting the "Generate Scripts Only" option in the Simulation Settings.
    Then go to <project_dir>/<project_name>.sim/simset/synth(impl)/func(timing)/ and edit the PRJ file to include the package file for compilation.
    After saving the modified PRJ file, manually run "compile.bat", "elaborate.bat" and "simulate.bat" from the command prompt to launch simulation.

 

This issue no longer occurs in Vivado 2015.1.

Thanks and Regards
Balkrishan
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Highlighted
Visitor
Visitor
20,244 Views
Registered: ‎03-14-2016

Re: <packagename> is not compiled in library xil_defaultlib

Hi Balkris,

 

Thanks for your answer - I saw the info you quoted elsewhere, but I'm not sure it really applies to this problem, as I am observing this problem in behaviourial simulation rather than post synthessis functional/timing sims, and as you say in your posting this no longer occours in Vivado 2015.1 (I'm a couple of versions on from there at 2015.4).

 

Thanks for your help.

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Xilinx Employee
Xilinx Employee
20,242 Views
Registered: ‎08-01-2008

Re: <packagename> is not compiled in library xil_defaultlib

http://www.xilinx.com/support/answers/58795.html

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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Newbie
Newbie
12,868 Views
Registered: ‎01-05-2018

Re: <packagename> is not compiled in library xil_defaultlib

In your cited "Source File Properties" window, try to tick the IS_GLOBAL_INCLUDE option:


vivado2.png

 

Highlighted
12,297 Views
Registered: ‎01-28-2018

Re: <packagename> is not compiled in library xil_defaultlib

Unfortunateley, the problem still persists in Vivado 2017.4.

 

In my case, I have defined very complex data structures in a VHDL package and it would be a real tedious work to flat down all these structures within the individual design files.

 

Another point to remark is: I tried to right-click on the package and then left click onto "Set Library". It always defaults to "work", even after selecting "xil-defaultlib" several times. This may be a reason for the problem?

 

Any ideas to fix this problem EXECPT "Avoid using constants etc defined in the package" or running the simulation manually (because I do not know where to find the button "Generate Scripts Only" in my simulation settings)???

 

Thanks in advance

Norbert

 

 

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Xilinx Employee
Xilinx Employee
12,277 Views
Registered: ‎09-25-2014

Re: <packagename> is not compiled in library xil_defaultlib

Hi @norbertreifschneider,

 

To generate scripts , use launch_simulation -scripts_only in the tcl console. Can you attach your compile.sh and .prj files generated in your project.sim/sim_1/behave/xsim folder?

 

Thanks,

Srimayee

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Highlighted
12,267 Views
Registered: ‎01-28-2018

Re: <packagename> is not compiled in library xil_defaultlib

Hi Srimayee,

 

I already took the work to replace all multi dimensional arrays by simple std_logic_vectors (so obviating the need to include the VHDL package defining them) and now I am currently testing post-implementation-simulation.

 

Thanks and regards

 

Norbert

 

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Explorer
Explorer
9,973 Views
Registered: ‎09-27-2013

Re: <packagename> is not compiled in library xil_defaultlib

Is there a usable fix for this, without rewriting tons of code?

 

This works fine in other simulators. It'd be nice if Vivado wasn't crapping out on things that are legal VHDL.

Highlighted
Visitor
Visitor
9,758 Views
Registered: ‎03-28-2018

Re: <packagename> is not compiled in library xil_defaultlib

Hello @balkris,

 

I'm using ISE 14.7 and I encountered this problem when I tried to use package files in my VHDL design. 

Is there a solution for it or can I use the same method as in vivado?

 

Thanks

 

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Observer
Observer
9,713 Views
Registered: ‎04-10-2018

Re: <packagename> is not compiled in library xil_defaultlib

Hi,

I've got the same issue with Vivado 2017.3 and I found a solution (I'm compiling everything in library work but I guess it works the same with library xil_defaultlib).

 

I initially had the package file added to the 'Design sources' folder only (sources panel -> libraries tab -> design sources -> vhdl -> work).

 

Than I added the same file to the 'Simulation-Only Sources' folder (sources panel -> libraries tab -> simulation-only sources -> sim_1 -> vhdl -> work), resulting in having the same file duplicated in the sources tab.

 

This fixed the problem.

 

Dario

 

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Observer
Observer
8,548 Views
Registered: ‎07-20-2017

Re: <packagename> is not compiled in library xil_defaultlib

I got this error in Vivado 2018.2 when using a custom VHDL package.  Synthesis and Implementation worked fine, but Behavioral Simulation failed.  The problem was with the compile order: the package was not compiled before the entity in which it was used.  I fixed it by manually moving the package source file to the top of the list under Sources | Compile Order | Design Sources.

It seems like Synthesis can figure out the package dependency but the Simulator can't...

Highlighted
Observer
Observer
8,484 Views
Registered: ‎04-10-2018

Re: <packagename> is not compiled in library xil_defaultlib

@clarkchris

I found an easier way to fix this that allows you to keep the automatic compile order.

I found out that enabling 'Include all design sources for simulation' in settings->simulation->advanced fixed permanently this problem for me. You now only need to make the synthesis working and the simulation compiler should work as well as it checks the same files.

Regards,

Dario

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8,134 Views
Registered: ‎05-03-2012

Re: <packagename> is not compiled in library xil_defaultlib

kudos to clarkchris.  compile order definitely matters for the simulator.  synthesis and implementation are less finicky.  Manual movement of source files works.  Vivado 2018.2.

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Visitor
Visitor
4,579 Views
Registered: ‎05-08-2018

Re: <packagename> is not compiled in library xil_defaultlib

I just wanna say that I'm working with Xilinx FPGAs for years and still can't really imagine how is it possible that such big company can provide such shitty development tool. It is slowest, most buggy and annoying IDE I've ever seen... Unfortunatelly there is no alternative... I hope that project managers responsible for that "thing" will get fired or moved to something more adequate for their competences (floor cleaning, making cofee; I don't want to drink that coffey though) and finally this app will go to the right direction. It's really a shame for Xilinx - they make such powerfull chips, but IDE feels like created by couple of kids that are beginning their "adventure" in software development! 

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4,452 Views
Registered: ‎01-28-2018

Re: <packagename> is not compiled in library xil_defaultlib

Hi again,

I must say that sellen is right.

My design worked fine until now.

I suddenly get this error again and this time I cannot fix it.

On the images attached you see that the package "RFSPack.vhd" is properly located within the "work" library. Nevertheless, the tools says "[Synth 8-4169] error in use clause: package 'rfspack' not found in library 'work' [FDRE_Reg1024_8RdWr_Shift.vhd":23]".

Any idea how to get rid of the f**ing and really annoying error message??

Norbert

 

ShitErr1.jpg
ShitErr2.jpg
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Scholar
Scholar
4,437 Views
Registered: ‎08-01-2012

Re: <packagename> is not compiled in library xil_defaultlib

@norbertreifschneider 

Maybe you're confused about the work library. Work is not a library itself - it is the current working library. Until recently (2017/18 I think) Xilinx got this wrong and build a specific library called work, which is against the VHDL spec.

You could almost think of "work" as the "local library". In your case, FDRE_Reg1024_8RdWr_Shift is in Xil_defaultlib and "rfspack" must not be in it, but some other library.

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Highlighted
4,307 Views
Registered: ‎07-08-2019

Re: <packagename> is not compiled in library xil_defaultlib

Facing the problem in 2018.2.2

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Highlighted
Contributor
Contributor
3,833 Views
Registered: ‎04-14-2008

Re: <packagename> is not compiled in library xil_defaultlib

 

Using Vivado 2019.1 and having this issue. The simulation sources compile order view (on the GUI) doesn't show many of the files actually needed, so I resorted to manually copying files from one fileset to the other, which seems to be working.

The base script is (assumes 'sim_1' as simulation sources and 'sources_1' for the design sources):

 

set existing_simulation_sources [get_files -of_objects [get_filesets sim_1] ]

foreach file [get_files -of_objects [get_filesets sources_1] -filter {FILE_TYPE == VHDL || FILE_TYPE == VERILOG || FILE_TYPE == SYSTEMVERILOG}] {
  set library [get_property LIBRARY [get_files -of_objects [get_filesets sources_1] $file]]
  
  # Don't add sources that are already on the list
  if { [lsearch -exact $existing_simulation_sources $file] == -1 {
    # Add the file into the simulation file set
    add_files -norecurse -fileset sim_1 [get_files -of_objects [get_filesets sources_1] $file]
  }
  # Set the library of the path *on the simulation sources fileset*
  set_property LIBRARY $library [get_files -of_objects [get_filesets sim_1] $file]
}

 

 

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Newbie
Newbie
2,749 Views
Registered: ‎06-26-2017

Re: <packagename> is not compiled in library xil_defaultlib

I am using vivado 18.3 and have performed all the suggestions above with no success.  

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Observer
Observer
556 Views
Registered: ‎03-21-2020

Re: <packagename> is not compiled in library xil_defaultlib

that's right. 

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