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Adventurer
Adventurer
269 Views
Registered: ‎09-15-2008

mark hdl record for debug

Hi,

I'm wondering if there's a way to mark for debug a signal whose type is user defined record.

Is it possible or shall I open the synthesized design and see how the record has been exploded?

Regards,

  Mariano

 

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4 Replies
Moderator
Moderator
234 Views
Registered: ‎09-15-2016

Re: mark hdl record for debug

Hi @mariano_severi,

Can you please open synthesized design and check if the signal you want to debug exists. 

Thanks & Regards,
Sravanthi B
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Scholar richardhead
Scholar
217 Views
Registered: ‎08-01-2012

Re: mark hdl record for debug

I have marked records for debug without a problem (including VHDL 2008 unconstrained types)

You have to mark the whole record though, you cannot mark individual members. If the record is rather large, this may have an effect on the layout/ routing as it will prevent optimization of the record.

I have done this using the mark_debug attribute in HDL.

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Explorer
Explorer
67 Views
Registered: ‎08-21-2013

Re: mark hdl record for debug

 

 


@richardhead wrote:You have to mark the whole record though, you cannot mark individual members. If the record is rather large, this may have an effect on the layout/ routing as it will prevent optimization of the record.

 


Agreed. Hopefully, Xilinx will add this ability at some point. The workarounds are very clumsy. 

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Scholar richardhead
Scholar
48 Views
Registered: ‎08-01-2012

Re: mark hdl record for debug

@corestar

While you have to mark an entire record for debug, you can manually remove the parts you dont want during the setup of debug.

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