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Observer
Observer
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Registered: ‎04-06-2018

math_real subprogram cos does not have a body

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Hi,

I have some code that runs through Synthesis but if I try to run a Simulation I get the following error message:

Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto b37f08351de449ef88bad2cdfa577b3d --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot fp_test_behav xil_defaultlib.fp_test -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-1402] subprogram cos does not have a body [C:/Xilinx/Vivado/2017.4/ids_lite/ISE/vhdl/src/ieee/math_real.vhd:439]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit fp_test in library work failed.

Which doesnt mean anything to me since the library is obviously there and I never touched it.

Also my project has a lot of VHDL Files and from the error message I cant tell where the error is thrown.

Any ideas how to fix this?

My system is windows 10. Language VHDL, Tool Vivado 2017.4

Thanks

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Mentor
Mentor
444 Views
Registered: ‎02-24-2014

Re: math_real subprogram cos does not have a body

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Xilinx has been distributing the source for math_real.vhd in the latest versions of Vivado, and you can also get it yourself at this URL:  https://standards.ieee.org/content/dam/ieee-standards/standards/web/download/1076.2-1996_downloads.zip

It might work better if you include the math_real-body.vhd file in your Vivado project.   Or try a newer version of Vivado.

Don't forget to close a thread when possible by accepting a post as a solution.

View solution in original post

4 Replies
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Moderator
Moderator
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Registered: ‎04-24-2013

Re: math_real subprogram cos does not have a body

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Hi @ghhhi ,

If you look in your project folder you will see a .sim directory e.g. //path_to/project_1/project_1.sim.

Within this there should be a sub folder that contains the compile.log, elaborate.log and simulate.log files.

Based on the message it looks like the elaboration was being run when the error was thrown, if you look in the elaborate.log file it should point you to the file that was being analysed.

Let me know if this helps.

Best Regards
Aidan

 

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Observer
Observer
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Registered: ‎04-06-2018

Re: math_real subprogram cos does not have a body

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Hello @amaccre ,

thanks for your reply. Unfortunately this didn't help since the message I posted is the exact same one as in the elaborate.log

compile.log only contains two lines

INFO: [VRFC 10-163] Analyzing VHDL file "C:/path_to_project/src/testbench/fp_test.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity fp_test

simulate.log doesnt exist, I guess because Vivado doesnt get that far.

So while I was at it, I checked the xvhdl.log in the sim_1/synth directory, which is created when I try to run a post synthesis simulation (which fails as well as the "normal" simulation.

There it tells me

INFO: [VRFC 10-307] analyzing entity fp_test
ERROR: [VRFC 10-706] formal use_mlt_for_addsub is not a generic [/path_to_proj/src/testbench/fp_test.vhd:136]
ERROR: [VRFC 10-1471] type error near true ; current type boolean; expected type string [/path_to_proj/src/testbench/fp_test.vhd:136]
ERROR: [VRFC 10-706] formal use_mlt_for_cmult is not a generic [/path_to_proj/src/testbench/fp_test.vhd:137]
ERROR: [VRFC 10-1471] type error near true ; current type boolean; expected type string [/path_to_proj/src/testbench/fp_test.vhd:137]
(....)
ERROR: [VRFC 10-706] formal xseries is not a generic [/path_to_proj/src/testbench/fp_test.vhd:143]
ERROR: [VRFC 10-706] formal nfft is not a generic [/path_to_proj/src/testbench/fp_test.vhd:144]
ERROR: [VRFC 10-1504] unit fp_test ignored due to previous errors [/path_to_proj/src/testbench/fp_test.vhd:51]
INFO: [VRFC 10-240] VHDL file /path_to_proj/src/testbench/fp_test.vhd ignored due to errors

which seems odd since my entity declaration looks like this:

entity fp23_logic is
    generic (
        USE_SCALE           : boolean:=TRUE;       --! use full scale rambs for twiddle factor
        USE_MLT_FOR_ADDSUB  : boolean:=TRUE;       --! Use DSP48E1/2 blocks or not for Add/Sub
       (...)
XSERIES : string:="7SERIES"; --! FPGA family: for 6/7 series: "7SERIES"; for ULTRASCALE: "ULTRA"; NFFT : integer:= 8 --! Number of FFT stages ); port ( .....)

and my instantiation in the testbench :

uut_fft: entity work.fp23_logic
    generic map (
        USE_SCALE           => TRUE,      --! use full scale rambs for twiddle factor
        USE_MLT_FOR_ADDSUB  => TRUE,      --! Use DSP48E1/2 blocks or not for Add/Sub
        (...)
XSERIES => "7SERIES", --! FPGA family: for 6/7 series: "7SERIES"; for ULTRASCALE: "ULTRA"; NFFT => NFFT_c --! Number of FFT stages ) port map (...)

Is this not how you use boolean?

Anyways so I go on and out-comment the generic map in the testbench to let my entity run with its generic-default values. "Normal" simulation has same results, post-synthesis simulation gets stuck at "Executeing elaborate step..." forever.

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Highlighted
Mentor
Mentor
445 Views
Registered: ‎02-24-2014

Re: math_real subprogram cos does not have a body

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Xilinx has been distributing the source for math_real.vhd in the latest versions of Vivado, and you can also get it yourself at this URL:  https://standards.ieee.org/content/dam/ieee-standards/standards/web/download/1076.2-1996_downloads.zip

It might work better if you include the math_real-body.vhd file in your Vivado project.   Or try a newer version of Vivado.

Don't forget to close a thread when possible by accepting a post as a solution.

View solution in original post

Observer
Observer
425 Views
Registered: ‎04-06-2018

Re: math_real subprogram cos does not have a body

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Thank you, including math_real and math_real-body files as "work" libraries is a workaround that lets it run through simulation.

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