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Contributor
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Registered: ‎08-29-2016

mipi_dphy_rx/tx simulation with Cadence Simvision

Hi,

 

I have generated the 'mipi_dphy_rx', and the 'mipi_dphy_tx' LogiCore IP, for the Ultrascale FPGA using Vivado design suite. I would like to simulate a design, with a controller of my own design, controlling the Tx, connected to the Rx.

 

I see that the 'pg202-mipi-dphy.pdf' document details a test-bench for the MIPI dphy, with the Tx IP connected to the RX IP. However, this section of the document is very short and not elaborated upon, nor can I find any testbench files in either the Tx or Rx IP that I have generated. 

 

I can see that Vivado has grouped some files under 'Synthesis' and others under 'SImulation'. 

 

My questions are : 

 

Is the test bench outlined in Ch.6 of the document above available in Vivado design suite ?

If I were to write my own test-bench, what files do I need to include in the mipi_dphy_tx/rx designs in order to do so with a third party simulator (e.g Cadence Incisive).

 

 

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Registered: ‎11-09-2015

Re: mipi_dphy_rx/tx simulation with Cadence Simvision

Hi @gmoore,

 

Generate the example design for the IP (add the IP to vivado > right click on the IP in the source window > open example design). You will have the test bench in the simulation sources in the example design project in vivado.

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎08-29-2016

Re: mipi_dphy_rx/tx simulation with Cadence Simvision

Hi Florentw,

 

thanks for that, I was able to simulate my design with the testbench as an example. 

 

I have been trying to get the Incisive 3rd party simulator working but I am encountering errors. The Tcl console output and the log file contents are attached below. 

 

I am using Vivado 2017.1 , and Incisive Version 15.20-s032. I am aware that the documentation says that the supported Incisive version is 15.20.014, however there should not be such a difference as to make 15.20-s032 incompatible ? 

 

There are some existing unresolved questions on the forums that I have already checked, and they seem to have the same issue : 

 

https://forums.xilinx.com/t5/7-Series-FPGAs/compile-simlib-error-in-14-3/td-p/538673

 

https://forums.xilinx.com/t5/Simulation-and-Verification/compile-simlib-error-again-after-INCISIV-version-fix/td-p/539099/page/2

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Registered: ‎08-29-2016

Re: mipi_dphy_rx/tx simulation with Cadence Simvision

Hi - any updates on this issue ? I would appreciate some more guidance on how to proceed

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Registered: ‎09-15-2016

Re: mipi_dphy_rx/tx simulation with Cadence Simvision

Hi @gmoore,

 

From the shared log files I see the following message:

ncvhdl_p: *F,NOLSTD: logical library name STD must be mapped to a design library [11.2].

 

Can you please check if the ncsim environment is set properly and if the following line exists in the cds.lib.

 

INCLUDE <IUS installation directory>/tools.lnx86/inca/files/cds.lib

 

Can you please try with the steps mentioned in the below forum post:

https://forums.xilinx.com/t5/Simulation-and-Verification/compile-simlib-error-again-after-INCISIV-version-fix/td-p/539099 

 

Hope this helps.

 

Thanks & Regards,

Sravanthi B

 

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Thanks & Regards,
Sravanthi B
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Contributor
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Registered: ‎08-29-2016

Re: mipi_dphy_rx/tx simulation with Cadence Simvision

Hi,

 

I tried the steps in the linked post - I added the 'include' line to the cds.lib file. As advised by the user in that thread, edited the '.cxl.vhdl.unisim.unisim.lin64.cmd' file to point the 'cds.lib' location to the parent directory of the cmd file, where it actually resides. When I run the cmd then, I get the following errors : 

 

.cxl.vhdl.unisim.unisim.lin64.cmd


ncvhdl(64): 15.10-s014: (c) Copyright 1995-2016 Cadence Design Systems, Inc.
/cad/adi/apps/xilinx/vivado/2017.1/Vivado/2017.1/data/vhdl/src/unisims/unisim_retarget_VCOMP.vhdp:
ncvhdl_p: *F,DLUNNE: Can't find STANDARD at /cad/adi/apps/cadence/incisive/linux/15.20-s30/tools.lnx86/inca/files/STD.
ncvhdl(64): 15.10-s014: (c) Copyright 1995-2016 Cadence Design Systems, Inc.
/cad/adi/apps/xilinx/vivado/2017.1/Vivado/2017.1/data/vhdl/src/unimacro/unimacro_VCOMP.vhd:
ncvhdl_p: *F,DLUNNE: Can't find STANDARD at /cad/adi/apps/cadence/incisive/linux/15.20-s30/tools.lnx86/inca/files/STD.
ncvhdl(64): 15.10-s014: (c) Copyright 1995-2016 Cadence Design Systems, Inc.
/cad/adi/apps/xilinx/vivado/2017.1/Vivado/2017.1/data/vhdl/src/unifast/primitive/DSP48E1.vhd:
ncvhdl_p: *F,DLUNNE: Can't find STANDARD at /cad/adi/apps/cadence/incisive/linux/15.20-s30/tools.lnx86/inca/files/STD.

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Registered: ‎08-29-2016

Re: mipi_dphy_rx/tx simulation with Cadence Simvision

Hi,

 

Are there any other steps for me to try ? the steps in the linked post are producing the error I posted above 

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