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Visitor mmonesh
Visitor
483 Views
Registered: ‎08-21-2019

missing gig_ethernet_pcs_pma_v16_1_2

Hi,

I have generated gig_ethernet_pcs_pma_0 (gmi - sgmi bridge ) using Vivado 2017.4.1. When iwas trying to compile it, by just running the lint.

I am getting following error

ncvhdl_p: *E,LIBNOM (/proj/garnet/users/mmonesh/garnet_fpga/design/peri_ss/ethernet_top/gmii_sgmii_bridge/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0_BaseX_Byte.vhd,112|35): logical library name must be mapped to design library [11.2].
use gig_ethernet_pcs_pma_v16_1_2.NativePkg.all;

This is because in one of the vhdl fille, it is using

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_UNSIGNED.all;
library UNISIM;
use UNISIM.vcomponents.all;
library gig_ethernet_pcs_pma_v16_1_2;
use gig_ethernet_pcs_pma_v16_1_2.NativePkg.all;

By using unisim_VCOMP.vhd 'library UNISIM" error is resolved. But i am not able to find any file which can solve the problem of "library gig_ethernet_pcs_pma_v16_1_2".

 

Can anyone please tell me which file should i use to resolve the above error??

 

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10 Replies
Moderator
Moderator
461 Views
Registered: ‎05-31-2017

Re: missing gig_ethernet_pcs_pma_v16_1_2

HI @mmonesh ,

Are you using the compatible IES version ?

Have you compiled the simulation libraries successfully & pointed them correctly for simulation?

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Visitor mmonesh
Visitor
447 Views
Registered: ‎08-21-2019

Re: missing gig_ethernet_pcs_pma_v16_1_2

Hi Shameera,

I am not using IES, i am using INCISIV (cadence) for lint checks, version 15.20.047.

You can go through logfile also which i am attacging here.

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Moderator
Moderator
431 Views
Registered: ‎05-31-2017

Re: missing gig_ethernet_pcs_pma_v16_1_2

HI @mmonesh,

I hope you mean to say that you are using "Incisive Enterprise Simulator", for which I have represented in the short notation as "IES".

So, before using the third-party simulators with Vivado we need to compile the simulation libraries. Have you compiled the simulation libraries successfully, can you please share the compile_simlib.log file ?

 

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Visitor mmonesh
Visitor
423 Views
Registered: ‎08-21-2019

Re: missing gig_ethernet_pcs_pma_v16_1_2

Hi Shameera,

Their is only one logfile which is getting generated currently, and that i had already shared with you, as before generating other logfile, error occurs.

Actually i was getting error for

library UNISIM;
use UNISIM.vcomponents.all;

also,

Error: ncvhdl_p: *E,LIBNOM (/proj/garnet/users/mmonesh/garnet_fpga/design/peri_ss/ethernet_top/gmii_sgmii_bridge/gig_ethernet_pcs_pma_0/gig_ethernet_pcs_pma_0_BaseX_Byte.vhd,110|13): logical library name must be mapped to design library [11.2]. use UNISIM.vcomponents.all;

and when i used the unisim_vcomp.vhd as:

-makelib UNISIM \
"/ltools/xilinx/Vivado/2017.4.1/data/vhdl/src/unisims/unisim_VCOMP.vhd" \
-endlib

that error is resolved.

So in a similar way for,

library gig_ethernet_pcs_pma_v16_1_2;
use gig_ethernet_pcs_pma_v16_1_2.NativePkg.all;

their will be some file as gig_ethernet_pcs_pma_v16_1_2.vhd or gig_ethernet_pcs_pma_v16_1_2.v, which will contain NativePkg,

In xilinx/ip/gig_ethernet_pcs_pmav16* area the file should be present, but i am seeing to see that i have /ltools/xilinx/Vivado/2017.4.1/data/ip/xilinx/gig_ethernet_pcs_pma_v16_1/hdl/gig_ethernet_pcs_pma_v16_1_rfs.vhd, which is not working.

I want to know where i can found the file "gig_ethernet_pcs_pma_v16_1_2.vhd". Or else suggest me which file i can refer where i can get NativePkg compatible with gig_ethernet_pcs_pma_v16_1_2??

 

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Moderator
Moderator
407 Views
Registered: ‎05-31-2017

Re: missing gig_ethernet_pcs_pma_v16_1_2

Hi @mmonesh ,

Can you please explain your flow ? I mean are you writing the custom scripts for running simulation in IES or else are you using the scripts generated by vivado ?

Ideally, before using any third-party simulation tools, we need to compile the simulation libraries. Please check page 15 of UG 900 regarding the same. The compile_simlib.log file will get generated after compiling the simulation libraries and would be present in the location from where you are compiling simulation libraries.

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Visitor mmonesh
Visitor
358 Views
Registered: ‎08-21-2019

Re: missing gig_ethernet_pcs_pma_v16_1_2

Hi shameera,

We have our own scripts for compilation and simulation, we don't use vivado generated script. And the simulation libraries are getting compiled properly, i am picking the libraries from unisim. We have many more IPs which are generated using vivado, and for them we didn't face any issues, this is the first IP, where we are facing issues.

And also one more thing i want to ask, for this ip all the generated RTL files are in verilog, and only one file in vhdl why is it so??

 

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Voyager
Voyager
308 Views
Registered: ‎10-12-2016

Re: missing gig_ethernet_pcs_pma_v16_1_2

Hi @shameera , 

Thank you very much for you are response. 

Me and  @mmonesh  are working. 

We compiled all Xilinx IP's to irun (cadance simulator), and pointing the compiled library. we tried this in the vivado GU I itself. 

when we are running the simulation using vivado simulator there is no issue, but getting library and some other issues if we use irun(IES-cadance) simulator. 

These are the different issues we are facing. 

1. attached irun.log (In this case we used same scripts which are generated by vivado for IES(cadance))

2. library issues as mentioned by @mmonesh , in the followin link(in this thread only)

https://forums.xilinx.com/t5/Simulation-and-Verification/missing-gig-ethernet-pcs-pma-v16-1-2/m-p/1019760#M27219xili

 

Any advice or help is highly appreciated. 

Regards, 

S Sampath

 

 

 

-Sampath
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Moderator
Moderator
293 Views
Registered: ‎09-15-2016

Re: missing gig_ethernet_pcs_pma_v16_1_2

Hi @ssampath ,

Can you please try exporting simulation scripts for your project from Vivado using the below command or go to file --> export --> export simulation and generate the scripts make sure you are pointing to the compiled libraries location using -lib_map_path option. Then run the generated scripts in standanlone IES simulator and check if you are still facing issues. 

export_simulation -lib_map_path "./compile_simlib/ies" -directory "./sim" -simulator ies -force 

For more information on this command, please refer the below user guide page#125,154:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug900-vivado-logic-simulation.pdf

If you are not facing any issues with the tool generated scripts then try comparing these scripts with your custom scripts and check if you are missing any commands.

Also, Please make sure that the simulation libraries are compiled without any issues.

Thanks & Regards,
Sravanthi B
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Voyager
Voyager
262 Views
Registered: ‎10-12-2016

Re: missing gig_ethernet_pcs_pma_v16_1_2

HI @bandi ,

Simulation is working now, but while synthesizing showing error as native library not found pls add the library.

RTL code: 

library gig_ethernet_pcs_pma_v16_1_2;

use gig_ethernet_pcs_pma_v16_1_2.NativePkg.all;  <= here am getting error.

 

Q1: In case of simulation i pointed compiled libraries but in case of synthesis how to point the specific library ?

Q2: i generated the etherner IP using vivado, the ip has some vhdl file and those having library includes. why vivado synthesis tool not able to find the required libraries ?

 

NOTE: Any help or advice is highly appreciated.

Regards,

Sampath sudi

-Sampath
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Moderator
Moderator
237 Views
Registered: ‎05-31-2017

Re: missing gig_ethernet_pcs_pma_v16_1_2

Hi @ssampath ,

Ideally, the IP's should get synthesized without any issues unless the user modified the IP generated HDL files.

Are you using any third-party synthesis tool for synthesizing the Xilinx IP's ?

If you are using vivado synthesis tool and facing this issue, you can cross-check by opening the IP example design and without doing any modifications to the IP generated HDL file the example design should synthesize without any issues.

 

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