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Contributor
Contributor
18,083 Views
Registered: ‎06-05-2010

modelsim simulation of Vivado encrypted IP

Using:

- Vivado v2013.2 (64-bit) Build 272601

- ModelSim PE 10.2b

 

After converting a design from ISE 14.4 to Vivado, then upgrading most of the Xilinx IP as recommended such as multipliers, divider, ten_gig_eth_pcs_pma (to name a few), I can't figure out how to simulate it.  What had been delivered as verilog models now appears to be encrypted VHDL.  For example, the free multiplier 12.0 core is encrypted preventing me from using it.

 

I followed all the Vivado docs, ran 'compile_simlib', etc., but the modelsim 'do' file it generates errors out when it attempts to compile the encrypted files.  Here's the error message:


vcom mult_gen_v12_0.vhd
# Model Technology ModelSim PE vcom 10.2b
# -- Loading package STANDARD
# ** Error: mult_s10_u16/mult_gen_v12_0/simulation/mult_gen_v12_0.vhd(46)): in protected region.
# ** Error: mult_gen_v12_0.vhd(46)): in protected region.
# ** Error: mult_gen_v12_0.vhd(46)): in protected region.
# ** Error: mult_gen_v12_0.vhd(46)): in protected region.
# ** Error:mult_gen_v12_0.vhd(46)): in protected region.
# C:/modeltech_pe_10.2b/win32pe/vcom failed.

 

According to one of the User Guides Xilinx IP (free IP as well apparently) is delivered using the IEEE P1735 encryption standard. 

 

Can someone explain how to use these files in a modelsim behavioral simulation please? 

 

Thanks,

Mike 

 


 

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31 Replies
Teacher muzaffer
Teacher
18,021 Views
Registered: ‎03-31-2012

Re: modelsim simulation of Vivado encrypted IP

I think you need to load a pli library called libxil_vsim.so for decryption to work. I am not sure about the details for modelsim flow.
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Visitor sagem95
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17,538 Views
Registered: ‎10-17-2013

Re: modelsim simulation of Vivado encrypted IP

Hello,
I have the same problem with Vivado v2013.2 and ModelSim SE 10.1d. when i try to compile the encrypted files.

Do you have resolve this mistake ? and How ?
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Moderator
Moderator
17,533 Views
Registered: ‎04-17-2011

Re: modelsim simulation of Vivado encrypted IP

For encrypted modules Modelsim wont be able to simulate it. If your design has encrypted modules, run Post-Synthesis Functional Simulation as it would take care of the same as you can Synthesize the files in Vivado without any issues.
Regards,
Debraj
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17,518 Views
Registered: ‎05-04-2009

Re: modelsim simulation of Vivado encrypted IP

these are bad news.

dvt_v4_0 have got the same problem in simulation.

vivado simulator does not have the same good feature than modelsim, how to solve this bad issue ?

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Xilinx Employee
Xilinx Employee
17,513 Views
Registered: ‎04-16-2012

Re: modelsim simulation of Vivado encrypted IP

Hi,

 

As mentioned by debraj in the previous post, did you try running post-synthesis simulation?

 

Thanks

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17,507 Views
Registered: ‎05-04-2009

Re: modelsim simulation of Vivado encrypted IP

why synthesize before simulation?

please let us know

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Xilinx Employee
Xilinx Employee
17,502 Views
Registered: ‎04-16-2012

Re: modelsim simulation of Vivado encrypted IP

Since the IP cores in the design are encrypted.

Thanks
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Teacher muzaffer
Teacher
17,483 Views
Registered: ‎03-31-2012

Re: modelsim simulation of Vivado encrypted IP

isn't the encryption in question the ieee standard encryption which most tools should be able to support ? does modelsim version in question support the ieee encryption?
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Moderator
Moderator
17,476 Views
Registered: ‎04-17-2011

Re: modelsim simulation of Vivado encrypted IP

Because the encryption done by one tool would not be supported by any other 3rd party tool as the key needs to be shared for decryption. Its same as if you generate a encrypted code in Cadence cannot be recognized in Modelsim. I hope this answers your questions.
Regards,
Debraj
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Teacher muzaffer
Teacher
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Registered: ‎03-31-2012

Re: modelsim simulation of Vivado encrypted IP

I am not sure whether you understand how the new ieee encryption system works. Here is the header for a xilinx encrypted block. See if you can make sense of it:

`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
n+htNXLSuU/3gao+frgxmXUQTli29QIRNGyQ0887RUnAC3AgiCZ1gTIU8irsVFEuTDgov7CTyrTj2Th3NXOyHg==

`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
UbcfJmAknb0eMNrzWO9mJ/9n9LXBVNcGsvOe7dGu/MMuQ3wKFfbcqBiv67hG056/LbOiX9My9K1m6b5jrwJxHZv7pDEneNyz3ROEqGXsxM1LHtn5gxpp2xGFNHHV5Ne/gtos38uCA3KRqoHGNWFYPRiDaX06ie1jO10Pm5sz8QU=

`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
JWJ25mlKufPgj2BD4GZrJr+krJHhQtbZnSImx+Ec+bXn9m1xsBWMNPNCuOwAjRRKeYdcq1TxYNJPghCHFqavug7WWKXiFG+V0oZLVjK2WSbLfgKCX1KPe7NXzv8XzYanBNpUMQS94bs5TtjA4Wty7FPygFkV6+hsv8+FrNR/9uoqCOt71+osj6Rrx5YCr6V7iH/oYTpT/7mPaj3S/qEwHiLpAwmn1ldJyErDP0vl/duRAAlBDdTKlse0jidlelrneBD72uNocpqsCw2m5hhOY4bz1o05SXEj4SkZe2/9+V+raBDw0+uGO2GfROa+F8pVC6nyv7nRy6CJWVKE5dxFjg==

`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
XM4lPtCEPUqzCZeRfc6+LnEZSsDbFSdUOyNB5fRscGqoGTu4liwHIAjww9FDOwWx5Y+UaJJ1OjNkA54uhSiU4nja01ClJke6fn4Dkd60o2nwgMyAJBuW1ZxMEiPSLVWxg/tn2+201Tc98F0786FLtYXv1chWdrSMb2OCXuk0LZc=

`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
t77k8TCMmHVA34DrEnwSwCxHWP5bV+6cfbB3HhMOheSDBvYlLfgxdG6ggtGXuEd1pQQXT3vJHzQBsT9071csCfKqX0zC2Eh89yFueQVbWl1x4KWJwZstJV7OyXUPsl5LyCVbTd4Z2t/sIpIkaIX/Sw1cV2oJNlQqsU5cfdz/LtgRm6suXzVrN0UfK5HApKrT4TBtMOf9CGuB8W0l9QpCkiwIe024AIMGZxjG6gvr54aaRTnPKdcmOrU0V0hBh2CsQSjgZVta0chk/g0z4VtfXzpJ5/R0REjTMjtVedbmIDjVEj63cOQvC50VFgxHxpbUJiNM+B1gty2jwksCbbCZrA==

`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 596442)
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Visitor gpsal99
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13,367 Views
Registered: ‎09-10-2013

Re: modelsim simulation of Vivado encrypted IP

That did not work. Any other suggestions?
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Xilinx Employee
Xilinx Employee
13,355 Views
Registered: ‎07-16-2008

Re: modelsim simulation of Vivado encrypted IP

Did you launch Modelsim from Vivado or outside?

If you launch Modelsim standalone and create a custom do file, ensure all the files for simulation are included.

 

Generally, Vivado IP simulation is supported by Modelsim.

If for some IPs behavioral simulation is not possible due to encryption, you'll need to run post-synthesis structral simulation.

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Observer emh_007
Observer
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Registered: ‎08-21-2013

Re: modelsim simulation of Vivado encrypted IP

Seriously?

 

I have a memory which is encrypted...  and I have to run a post-synthesis simulation just because of a memory?

And this is not even the part of the circuit I want to simulate/ modify...

 

There is no other way?

 

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Teacher muzaffer
Teacher
12,588 Views
Registered: ‎03-31-2012

Re: modelsim simulation of Vivado encrypted IP

I think there is misleading information in many of the previous posts here. There is significant amount encryption key sharing between simulation vendors and/or encryption is done with public keys and decryption is done by private keys so that simulation of blocks encrypted by another vendor is possible withe the most recent encryption standards.

Also specifically for the question of simulating with post-synthesis output: one does not need to do this for all the blocks. You can generate post-synthesis code for the encrypted blocks only and use RTL for the remaining system if encryption compatibility is an issue.
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Visitor job_efi
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Registered: ‎06-08-2014

Re: modelsim simulation of Vivado encrypted IP

I am trying to simulate a fifo. Modelsim failed to build LIB fifo_generator_v12_0 due to the encrypted part of shft_wrapper.vhd.  How can I generate a post-synthesis code for this fifo? (vivado 14.1 and modelsim se10.3a)   thanks 

 
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Xilinx Employee
Xilinx Employee
12,525 Views
Registered: ‎02-06-2013

Re: modelsim simulation of Vivado encrypted IP

Hi

 

Check this below link for the library issue.

 

http://forums.xilinx.com/t5/Simulation-and-Verification/I-need-to-compile-blk-mem-gen-v8-2-with-Modelsim/m-p/467476#M9950

Regards,

Satish

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Moderator
Moderator
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Registered: ‎04-17-2011

Re: modelsim simulation of Vivado encrypted IP

@job_efi If you still have questions after the last suggestion given to you, I would recommend opening a new topic with your query.

Regards,
Debraj
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Visitor job_efi
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Registered: ‎06-08-2014

Re: modelsim simulation of Vivado encrypted IP

Thanks for help.

I think my case is similar to this topic. It is not that Modelsim can't find the files to simulate. It is the encrpted part of certain module that blocks the compiling. My design includes fifos.  How do you simulate it in the normal case?

 

I invoked Modelsim from vivado and used the do file generated by vivado. 

 

 

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Moderator
Moderator
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Registered: ‎04-17-2011

Re: modelsim simulation of Vivado encrypted IP

What is the message you are seeing? It does work properly.
Regards,
Debraj
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Visitor sajith.k
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Registered: ‎09-10-2012

Re: modelsim simulation of Vivado encrypted IP

I also had the same problem of "Protected region" during modelsim  'stand alone' simulation. But it was solved when i mapped compiled libraries unisim,unisims_ver..etc  in my local modelsim.ini file. Those who are stuck on, have a try

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Contributor
Contributor
10,120 Views
Registered: ‎06-05-2010

Re: modelsim simulation of Vivado encrypted IP

This post doesn't seem to address the original issue I had and still have.  I've since upgraded to 2014.2 and am trying to simulate a design using basic FIFO generated from Vivado Block Memory Generator.  It synthesizes ok but modelsim errors out complaining about a protected region.  The transript is further below.

 

I envoked things from within Vivado and let it create it's own 'do' file, then let it envoke modelsim.  Here's the line Vivado created in it's own 'do' file (minus the full directory path)..

 

  vcom  -work blk_mem_gen_v8_2 -2002 <full directory path>/blk_mem_gen_v8_2.vhd"

 

Vivado created the file 'blk_mem_gen_v8_2.vhd' and then has modelsim try to compile it.  That file is encrypted which causes the modelsim error. 

 

I've read through docs and posts and am still trying to get a clear answer to this. 

 

In summary, Vivado generates the block ram IP, creates the 'blk_mem_gen_v8_2.vhd' file, then generates a 'do' file instructing modelsim to compile it.  Everything is Vivado driven so it appears to be stepping on it's own foot. 

 

Can someone explain? 

 

Thanks!

 

 

# Model Technology ModelSim PE vcom 10.2c Compiler 2013.07 Jul 18 2013
# -- Loading package STANDARD
# ** Error: (vcom-19) Failed to access library 'synopsys' at "synopsys".
#
# No such file or directory. (errno = ENOENT)
# ** Error: vhdl_src/synopsys/mti_std_logic_misc.vhd(46)): in protected region.
# ** Error: vhdl_src/synopsys/mti_std_logic_misc.vhd(46)): in protected region.
# ** Error: vhdl_src/synopsys/mti_std_logic_misc.vhd(46)): in protected region.
###### c:/Users/gulottm/MyWork/Projects/Odin/FPGA_work/WDU/WDU_FPGA_ver1/Artix_vivado/trunk/ip/dpram_128x19/blk_mem_gen_v8_2/simulation/blk_mem_gen_v8_2.vhd(46)): <in protected region>** Error: c:/Users/gulottm/MyWork/Projects/Odin/FPGA_work/WDU/WDU_FPGA_ver1/Artix_vivado/trunk/ip/dpram_128x19/blk_mem_gen_v8_2/simulation/blk_mem_gen_v8_2.vhd(46)): in protected region.
# ** Error: C:/modeltech_pe_10.2c/win32pe/vcom failed.
# Error in macro C:\Users\gulottm\MyWork\Projects\Odin\FPGA_work\WDU\WDU_FPGA_ver1\Artix_vivado\trunk\par\project_1\project_1.sim\sim_1\behav\wdu_top.do line 40
# C:/modeltech_pe_10.2c/win32pe/vcom failed.
#     while executing
# "vcom  -work blk_mem_gen_v8_2 -2002 "c:/Users/gulottm/MyWork/Projects/Odin/FPGA_work/WDU/WDU_FPGA_ver1/Artix_vivado/trunk/ip/dpram_128x19/blk_mem_gen_v..."

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Xilinx Employee
Xilinx Employee
10,110 Views
Registered: ‎07-16-2008

Re: modelsim simulation of Vivado encrypted IP

From the log information, the root cause seems to be the failure to access the standard package.

 

# -- Loading package STANDARD
# ** Error: (vcom-19) Failed to access library 'synopsys' at "synopsys".

# No such file or directory. (errno = ENOENT)

 

If you have a look at the modelsim.ini in Modelsim install directory, you'll see synopsys library mapping in [library] section.

synopsys = $MODEL_TECH/../synopsys

 

Please ensure the modelsim.ini used in the current run contains the appropriate Modelsim default libraries.

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Participant randycason
Participant
7,951 Views
Registered: ‎08-25-2008

Re: modelsim simulation of Vivado encrypted IP

That worked for me as well, thanks.

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Visitor adrianperez
Visitor
7,192 Views
Registered: ‎04-17-2014

Re: modelsim simulation of Vivado encrypted IP

Hello everybody,

 

I am compiling a simulation file generated in Vivado.

The IP I have generated is the 1000BaseX-SGMII Xilinx IP, and the simulation file I am trying to compile is:

gig_ethernet_pcs_pma_v14_3_rfs.vhd

 

When generating the output files for the core, the file is located in: <ip_name>\gig_ethernet_pcs_pma_v14_3\hdl

 

I have generated the simulation scripts, and the file is compiled the first (before the other simulation files)

When I launch the simulation script, the following error appears :

 

* Error: <path_for_ip>/gig_ethernet_pcs_pma_v14_3/hdl/gig_ethernet_pcs_pma_v14_3_rfs.vhd(46): in protected region.

 

I think that is the same error which has happened to to the other people.

 

Does anyone what could be the cause for this error ?

 

The Modelsim version I use is 10.2

 

Many thanks and kind regards

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Observer mofsam
Observer
7,144 Views
Registered: ‎10-01-2015

Re: modelsim simulation of Vivado encrypted IP

Hi

running into the same situation. Its annoying that i have to go through synthesis to get a model that can simulate. In fact I have two Vivado projects in which a FIFO is simualted fine and inanother I get the 'protected' message.

 

So what is the simualtion degradation of running a post synthesis functional simulation?

Isnt it better to use inferred code and hence bypass all of this.

I could understand this for a major IP but Fifos i'm at a loss what really needs to be encryted.

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Observer mofsam
Observer
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Registered: ‎10-01-2015

Re: modelsim simulation of Vivado encrypted IP

You will have to create a post synthesis functional model and run that. I
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Adventurer
Adventurer
6,618 Views
Registered: ‎01-27-2008

Re: modelsim simulation of Vivado encrypted IP

Folks,

There's a much simpler way and I am not sure it was clearly indicated in the thread yet.

I haven't seen this pointed out in other threads either.

 

You don't need to work with their encrypted IP, you get a netlist that is dependent on unisim(s_ver).

 

When you generate the IP (at least fifo_generator), in the top level IP directory, you get a file that titled something like this:

<ip_name>-sim_netlist.[v,vhd]

 

This builds into a bunch of data (compile it into your proper ip version library (for instance, mine is fifo_generator_v13_0_1).

 

This should work just fine with any simulator and is simple. Enough.

 

Best,

Jerry

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Visitor cfswanson
Visitor
6,499 Views
Registered: ‎04-22-2010

Failed to open <protected> file

Support,

I am getting similar errors when running Vivado 2015.2 and Modelsim DE 10.4c

 

# ** Fatal: (vsim-7) Failed to open <protected> file "<protected>" in <protected> mode.
# No such file or directory. (errno = ENOENT)
# Time: 0 ps Iteration: 0 Protected: /noc_block_Receiver/inst_axi_fir/<protected>/<protected>/<protected>/<protected> File: /home/craig/uhd/rfnoc-devel/usrp3/lib/rfnoc/noc_block_Receiver_tb/build-ip/xc7k410tffg900-2/axi_fir/fir_compiler_v7_2/hdl/fir_compiler_v7_2_vh_rfs.vhd Line: UNKNOWN
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./runsim.do PAUSED at line 17

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Visitor j.herbert1
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6,239 Views
Registered: ‎03-11-2015

Re: modelsim simulation of Vivado encrypted IP

@olupj, unfortunately that doesn't seem to be true. I just tried to open the "...sim_netlist.v" file generated by the Xilinx Binary Counter IP, and it is basically just encrypted verilog. The VHDL file is encrypted too. I figured this was one of the simplest IPs and so wouldn't be protected.

 

If you know how to make it output unencrypted verilog for functional simulation, I'm all ears!

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