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makni
Adventurer
Adventurer
21,205 Views
Registered: ‎12-26-2013

modelsim: (vsim-3053) Illegal output or inout port connection

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Hi everybody,

 

I'm using ModelSim PE Student Edition 10.3a and I'm trying to run a TCL script under ModelSim,

 

The problem is when running this command using the tcl script: vsim work.Test_openFIRE , I'm getting this error:

# ** Error: (vsim-3053) simulation.v(30): Illegal output or inout port connection for "port 'dmem_addr'".

please find attached my tcl script and simulation.v files.

Many thanks in advance.

 

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pulim
Xilinx Employee
Xilinx Employee
29,319 Views
Registered: ‎02-16-2014

Hi,

 

Instead of positional association can you try using named assosciation for module instantiation as below?

 

openfire_cpu openfire_cpu(
.clock(clock), .reset(reset),
.dmem_addr(dmem_addr), .dmem_data_in(dmem_data_in), .dmem_data_out(dmem_data_out),
.dmem_we(dmem_we), .dmem_re(dmem_re), .dmem_input_sel(dmem_input_sel), .dmem_done(dmem_done),
.imem_addr(imem_addr), .imem_data_in(imem_data_in), .imem_re(imem_re), .imem_done(imem_done)
);

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pulim
Xilinx Employee
Xilinx Employee
21,198 Views
Registered: ‎02-16-2014

Hi,

 

In test bench you have declared dmem_addr as wire. It should be declared as reg since it is a input to your design.

If  signal in your design is declared as input then in your test bench you should define it as reg other wise define it as wire.

makni
Adventurer
Adventurer
21,187 Views
Registered: ‎12-26-2013

Hi,

 

 

Thanks for your reply, but dmem_addr is an output and not a input to my design. So, in testbench should be declared as wire!

ashishd
Xilinx Employee
Xilinx Employee
21,180 Views
Registered: ‎02-14-2014

Hi,

 

There are still some missing files in your attached code. Can you please archieve the entire project and attach it?  

Regards,
Ashish
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makni
Adventurer
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Registered: ‎12-26-2013

You can find the missing files in this .rar.

Thanks.

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makni
Adventurer
Adventurer
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Registered: ‎12-26-2013

Below are the errors generated when running the tcl script using modelsim:

# vsim work.Test_openFIRE
# Start time: 13:30:49 on May 15,2014
# Loading work.Test_openFIRE
# Loading work.openfire_cpu
# Loading work.openfire_fetch
# Loading work.openfire_decode
# Loading work.openfire_execute
# Loading work.openfire_alu
# Loading work.openfire_compare
# Loading work.openfire_regfile
# Loading work.openfire_rf_sram
# Loading work.openfire_pipeline_ctrl
# ** Warning: (vsim-3017) simulation.v(30): [TFMPC] - Too few port connections. Expected 14, found 13.
# 
#         Region: /Test_openFIRE/openfire_cpu
# ** Warning: (vsim-3015) simulation.v(30): [PCDPC] - Port size (1) does not match connection size (32) for port 'interrupt'. The port definition is at: rtl/openfire_cpu.v(49).
# 
#         Region: /Test_openFIRE/openfire_cpu
# ** Error: (vsim-3053) simulation.v(30): Illegal output or inout port connection for "port 'dmem_addr'".
# 
#         Region: /Test_openFIRE/openfire_cpu
# ** Warning: (vsim-3015) simulation.v(30): [PCDPC] - Port size (32) does not match connection size (1) for port 'dmem_data_out'. The port definition is at: rtl/openfire_cpu.v(58).
# 
#         Region: /Test_openFIRE/openfire_cpu
# ** Warning: (vsim-3015) simulation.v(30): [PCDPC] - Port size (1) does not match connection size (2) for port 'dmem_re'. The port definition is at: rtl/openfire_cpu.v(59).
# 
#         Region: /Test_openFIRE/openfire_cpu
# ** Error: (vsim-3053) simulation.v(30): Illegal output or inout port connection for "port 'dmem_input_sel'".
# 
#         Region: /Test_openFIRE/openfire_cpu
# ** Warning: (vsim-3015) simulation.v(30): [PCDPC] - Port size (2) does not match connection size (1) for port 'dmem_input_sel'. The port definition is at: rtl/openfire_cpu.v(59).
# 
#         Region: /Test_openFIRE/openfire_cpu
# ** Warning: (vsim-3015) simulation.v(30): [PCDPC] - Port size (1) does not match connection size (32) for port 'dmem_done'. The port definition is at: rtl/openfire_cpu.v(59).
# 
#         Region: /Test_openFIRE/openfire_cpu
# ** Error: (vsim-3053) simulation.v(30): Illegal output or inout port connection for "port 'imem_addr'".
# 
#         Region: /Test_openFIRE/openfire_cpu
# ** Warning: (vsim-3015) simulation.v(30): [PCDPC] - Port size (32) does not match connection size (1) for port 'imem_data_in'. The port definition is at: rtl/openfire_cpu.v(60).
# 
#         Region: /Test_openFIRE/openfire_cpu
# ** Error: (vsim-3053) simulation.v(30): Illegal output or inout port connection for "port 'imem_re'".
# 
#         Region: /Test_openFIRE/openfire_cpu
# ** Warning: (vsim-3722) simulation.v(30): [TFMPC] - Missing connection for port 'imem_done'.
# 
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./launchSim.tcl PAUSED at line 21

 i would appreciate any help on this.

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pulim
Xilinx Employee
Xilinx Employee
29,320 Views
Registered: ‎02-16-2014

Hi,

 

Instead of positional association can you try using named assosciation for module instantiation as below?

 

openfire_cpu openfire_cpu(
.clock(clock), .reset(reset),
.dmem_addr(dmem_addr), .dmem_data_in(dmem_data_in), .dmem_data_out(dmem_data_out),
.dmem_we(dmem_we), .dmem_re(dmem_re), .dmem_input_sel(dmem_input_sel), .dmem_done(dmem_done),
.imem_addr(imem_addr), .imem_data_in(imem_data_in), .imem_re(imem_re), .imem_done(imem_done)
);

View solution in original post

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ashishd
Xilinx Employee
Xilinx Employee
21,115 Views
Registered: ‎02-14-2014

Hi @makni ,

 

I have downloaded your design and tried to simulate it. When I checked it with Vivado 2014.1, I could find only one error with your design. If you check line #157 of sp3dk_simulator.v file, it is

 

reg [31:0] memory[`MAX_SIMULATION_SRAM];

 

For this line, simulator is showing error as

Error : Single value range only allowed in system verilog.

 

If you modify this line to specify proper range for memory array as

reg [31:0] memory[`MAX_SIMULATION_SRAM:0];

 

then I am able to launch the simulator GUI without any errors. Check the snapshot for your reference.

 

sim_gui.png

 

Regards,
Ashish
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makni
Adventurer
Adventurer
21,111 Views
Registered: ‎12-26-2013

Hi, 

 

Thanks a lot for your help.

I'm really very grateful.

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vineeshvs
Observer
Observer
3,603 Views
Registered: ‎11-26-2018

Is this problem resolved by using named association?

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