03-21-2020 01:05 PM
Hello, I have the Ready signal (please see attached files) which is must be last a single clock cycle to indicate that the output data are ready to be read. I got this signal correct when I use the behavioral simulation but when I use the post route simulation, I got multiple pulses for the Ready signal, which is not right.
any ideas about what causes this?
06-25-2020 05:46 AM
Post-route simulation uses xilinx primitives. If it is timing simulation then hold and setup time delays should be considered. Will it be possible for you to share your design?
06-25-2020 06:52 AM
"I got multiple pulses for the Ready signal, which is not right."
Why is not right ?
In a synchronous circuit it is normal for the signals to have glitch.
The only important thing is that they meet setup/hold times.