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Visitor
Visitor
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Registered: ‎03-18-2020

multiple pulses when using the post-route simulation

Hello,  I have the Ready signal (please see attached files) which is must be last a single clock cycle to indicate that the output data are ready to be read. I got this signal correct when I use the behavioral simulation but when I use the post route simulation,  I got multiple pulses for the Ready signal, which is not right.

any ideas about what causes this?

many thanks,

behavioural simulation.png
post route simulation .png
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Xilinx Employee
Xilinx Employee
185 Views
Registered: ‎05-01-2019

Hi,

Post-route simulation uses xilinx primitives. If it is timing simulation then hold and setup time delays should be considered. Will it be possible for you to share your design?

Thanks,

Harika.

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Voyager
Voyager
174 Views
Registered: ‎06-20-2012

@Sultan1 

"I got multiple pulses for the Ready signal, which is not right."

Why is not right ?

In a synchronous circuit it is normal for the signals to have glitch.

The only important thing is that they meet setup/hold times.

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