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Newbie jonar1995
Newbie
972 Views
Registered: ‎02-08-2018

my simulation wont run. Please help

i have made a very simple VHDL program using a easy starter guide. When i clicked run simulation the program wont go past the loading.. i have tried many different codes and this allways happens.. Here is a picture

simmulasjon.png

 

My VHDL code:

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;



entity AND_GATE is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           c : out STD_LOGIC);
end AND_GATE;

architecture Behavioral of AND_GATE is

begin

c <= a AND b;

end Behavioral;

 

 

My Testbench:

 

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity AND_GATE_tb is
end;

architecture bench of AND_GATE_tb is

  component AND_GATE
      Port ( a : in STD_LOGIC;
             b : in STD_LOGIC;
             c : out STD_LOGIC);
  end component;

  signal a: STD_LOGIC;
  signal b: STD_LOGIC;
  signal c: STD_LOGIC;

begin

  uut: AND_GATE port map ( a => a,
                           b => b,
                           c => c );

  stimulus: process
  begin
 
    a <= '0';
    b <= '0';
    wait for 10 ns;
    a <= '1';
    b <= '0';
    wait for 10 ns;
    a <= '0';
    b <= '1';
    wait for 10 ns;
    a <= '1';
    b <= '1';
    wait for 10 ns;
    a <= '0';
    b <= '0';
    
 

    wait;
  end process;


end;

 

 

 

 

Tags (1)
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4 Replies
Scholar dpaul24
Scholar
959 Views
Registered: ‎08-07-2014

Re: my simulation wont run. Please help

@jonar1995,

 

The XSIM compiler is your 1st friend, are looking at the compiler generated messages?

 

Moreover....

 

entity AND_GATE_tb is
end;

should be -

entity AND_GATE_tb is
end AND_GATE_tb;

 

Similar problem when you are ending/closing  architecture Behavioral of AND_GATE is

 

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Newbie jonar1995
Newbie
954 Views
Registered: ‎02-08-2018

Re: my simulation wont run. Please help

i cant look annywhere because the whole program is stuck in loading simulation..

0 Kudos
Scholar dpaul24
Scholar
950 Views
Registered: ‎08-07-2014

Re: my simulation wont run. Please help

If you can't kill Vivado, then please open your source code in a separate text editor and check.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
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Moderator
Moderator
897 Views
Registered: ‎04-24-2013

Re: my simulation wont run. Please help

Hi @jonar1995,

 

Welcome to VHDL in VIvado, here are a few tips that might make it easier for you.

 

Vivado has language templates built in that you can fill out, this can make it easier to avoid syntax errors.

Having said that copying and pasting code is frequently not your friend.

 

Template.PNG

 

You can also check the syntax of your design at any stage using the check_syntax command in the tcl console e.g.

 

check_syntax
INFO: [Vivado 12-4796] No errors or warning reported.

 

Btw I ran your code in the simulator and it completed as expected.

 

Best Regards
Aidan

 

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