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Contributor
Contributor
5,945 Views
Registered: ‎04-22-2014

netlist simulation

For FPGA synthsis, I am using synopsys synplify tool 2013.

And for the reset of things (BUILD, Place and Route and Timing) using ISE tool

What are the inputs required to simulate the  Post synthesis and Post P&R netlist.

 

When i am tried to complie the post synthesis netlist ( synplify output  *.vm file is move to *.v file) with Xilinx unisim libs and secureip libs getting the following error

 

ncelab:  *E  ERRIPR:  error with in protected source code.

 

Kindly help me.

 

 

Thanking you,

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2 Replies
Moderator
Moderator
5,932 Views
Registered: ‎01-16-2013

Re: netlist simulation

Hello,

This is simulation query please ask in simulation forum you will get better help there.

Thanks,
Yash
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Xilinx Employee
Xilinx Employee
5,925 Views
Registered: ‎09-20-2012

Re: netlist simulation

Hi,

 

Which version of IES are you using? Is it supported with the ISE version you are using? You can refer to synthesis and simulation Design guide for supported version details.

 

It looks like you are using multiple step process. Did you pre-compile the libraries for IES using compxlib tool?

 

Refer to Appendix-B of http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/sim.pdf for more details.

 

Thanks,

Deepika.

 

 

Thanks,
Deepika.
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