01-11-2018 02:18 PM
Just a report.
In Vivado 2017.3, if I write a function that is impure, without identifying it as impure, the editor will correctly flag the problem if I access a shared variable in the function not flagged as being impure.
However, the actual simulator will still simulate it just fine.
I'm not sure if this is a bug or a feature, but it seems like the guys who are writing the Vivado editor are parsing VHDL more pedantically than the simulator's analysis engine.
Or you could say this is a feature of the simulator, intrinsically treating the unmarked but still impure function as impure without the hassle of requiring the designer to type the keyword impure.
01-12-2018 01:28 PM
Its breaking the LRM, so its a bug!
It wouldnt be portable to other vendors.
I tend to agree, but was hedging a bit.