UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Reply

parsing impure functions in vivado editor vs. vivado simulator

Accepted Solution Solved
Highlighted
Observer
Posts: 49
Registered: ‎06-20-2017
Accepted Solution

parsing impure functions in vivado editor vs. vivado simulator

Just a report. 

 

In Vivado 2017.3, if I write a function that is impure, without identifying it as impure, the editor will correctly flag the problem if I access a shared variable in the function not flagged as being impure.

 

However, the actual simulator will still simulate it just fine.

 

I'm not sure if this is a bug or a feature, but it seems like the guys who are writing the Vivado editor are parsing VHDL more pedantically than the simulator's analysis engine.

 

Or you could say this is a feature of the simulator, intrinsically treating the unmarked but still impure function as impure without the hassle of requiring the designer to type the keyword impure.

*** Mike Morgan. Please note that many of us who help, or try to help, are mere FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***

How many kudos does it take to win a Xilinx t-shirt?

Accepted Solutions
Observer
Posts: 43
Registered: ‎08-01-2012

Re: parsing impure functions in vivado editor vs. vivado simulator

Its breaking the LRM, so its a bug!

It wouldnt be portable to other vendors.

View solution in original post


All Replies
Observer
Posts: 43
Registered: ‎08-01-2012

Re: parsing impure functions in vivado editor vs. vivado simulator

Its breaking the LRM, so its a bug!

It wouldnt be portable to other vendors.

Observer
Posts: 49
Registered: ‎06-20-2017

Re: parsing impure functions in vivado editor vs. vivado simulator


richardhead wrote:

Its breaking the LRM, so its a bug!

It wouldnt be portable to other vendors.


I tend to agree, but was hedging a bit.

*** Mike Morgan. Please note that many of us who help, or try to help, are mere FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***

How many kudos does it take to win a Xilinx t-shirt?