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Visitor
Visitor
5,242 Views
Registered: ‎04-14-2013

post place and root simulation

hi to all,

please i have a problem in clk_period, this is my code VHDL:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity essai_fil is
    Port ( clk : in  STD_LOGIC;
           d_in : in  STD_LOGIC;
           d_out : out  STD_LOGIC);
end essai_fil;

architecture Behavioral of essai_fil is

begin

  process(clk)--processus1
begin
if (clk'event and clk='1')then
  
         d_out <= d_in;
       end if ;
     end process;
   
end Behavioral;

 and this is the testbench generate automatically by xilinx: and it gives for clk_period =10 ns

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

 
ENTITY test_fil IS
END test_fil;
 
ARCHITECTURE behavior OF test_fil IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT essai_fil
    PORT(
         clk : IN  std_logic;
         d_in : IN  std_logic;
         d_out : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal d_in : std_logic := '0';

 	--Outputs
   signal d_out : std_logic;

   -- Clock period definitions
   constant clk_period : time := 100 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: essai_fil PORT MAP (
          clk => clk,
          d_in => d_in,
          d_out => d_out
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
	wait for Clk_period;
        
        d_in <= '1';
        wait for Clk_period;
        d_in <= '1';

      wait;
   end process;

END;

 and the post and route simulation give this result :

image2.png

please can any one explain to me why this late of output, ?????? it is from clk_period?

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4 Replies
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Xilinx Employee
Xilinx Employee
5,240 Views
Registered: ‎01-03-2008

This is a duplicate thread to: http://forums.xilinx.com/t5/Timing-Analysis/Timing-for-shift-register/m-p/312401#U312401

and

http://forums.xilinx.com/t5/New-Users-Forum/Timing-Simulation-X-values-even-with-SLOW-clock/m-p/312453#M3973

 

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Too many results? Try adding site:www.xilinx.com
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Professor
Professor
5,235 Views
Registered: ‎08-14-2007

I'm not sure if this applies to VHDL simulation, but at least in the Verilog versions, there

is an "under the hood" GSR that asserts for 100 ns at the start of simulation.  If any of

the simulation primitives rely on GSR, then this could explain the 100 ns delay.  You

could test this theory by delaying your input for at least 100 ns before setting it high and

then look to see if the delay was what you expected.

-- Gabor
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Visitor
Visitor
5,214 Views
Registered: ‎04-14-2013

can any one explain to me what's the value adequate of clk_period ? that depends on what ? 

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Visitor
Visitor
5,171 Views
Registered: ‎04-14-2013

thanks Gabor for you ansewer it's very imporatnt :)

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