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Visitor
Visitor
8,101 Views
Registered: ‎02-04-2009

post-route simulation with jitter

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Hi everybody i am running a project and i want my input clocks to have jitter, so i go to user constraints\create time constraints and i set clock period and input jitter at a value. After that i create a testbench with the same values for my clocks and then i run post-route simulation. I have noticed that input clock signals at the simulation do not have any variation at their period so they do not seem to have jitter. Is this normal? Or i should do something else so my input clocks have jitter?How do i understand that the tool takes into account my constraints at post-route simulation?  Thanks in advance for your answers!

 

P.S. I use xilinx ise simulator  for post-route simulation

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Xilinx Employee
Xilinx Employee
9,529 Views
Registered: ‎08-13-2007

Re: post-route simulation with jitter

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It isn't my solution, but I've seen this approach suggested before.

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;

entity JITTER_TB is
end JITTER_TB;

architecture TB of JITTER_TB is
  constant tHCLK:TIME:=1000 ps; -- 500.0 MHz
  constant tJMAX:TIME:=100 ps;  -- maximum jitter amplitude
  signal CLK:STD_LOGIC:='1';    -- clean clock
  signal CLKJ:STD_LOGIC;        -- jittery clock
begin
-- clean clock
  CLK<=not CLK after tHCLK;
-- clock with jitter
  process
    variable Seed1:INTEGER:=1234;
    variable Seed2:INTEGER:=5678;
    variable R:REAL:=0.0;
  begin
    CLKJ<=transport CLK after R*tJMAX;
    UNIFORM(Seed1,Seed2,R);
    wait until CLK'event;
  end process;
end TB;

 

Cheers,

bt

 

-- credit to cb at xilinx

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Xilinx Employee
Xilinx Employee
8,091 Views
Registered: ‎08-13-2007

Re: post-route simulation with jitter

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This is normal.

The SYSTEM_JITTER influences the timing analysis of the design - as described in the constraints guide (cgd.pdf).

This does not effect your back-annotated simulation as the clocks are driven by your testbench. If you want to simulate jitter - you will have to model your clock appropriately in your testbench.

 

bt

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Visitor
Visitor
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Registered: ‎02-04-2009

Re: post-route simulation with jitter

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ok thanks. but how i can model my clock appropriately in my testbench?
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Xilinx Employee
Xilinx Employee
8,056 Views
Registered: ‎08-13-2007

Re: post-route simulation with jitter

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The basic idea would be to add or subtract an amount every clock according to a specific distribution.

I don't think most people go to these lengths.

 

One approach would be to use the UNIFORM library from ieee.math_real.all (assuming VHDL), multiply it by a scaling factor and use it to adjust your clock every period in your generating process.

 

bt

Message Edited by timpe on 03-05-2009 08:06 PM
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Visitor
Visitor
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Registered: ‎02-04-2009

Re: post-route simulation with jitter

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I am sorry if i become annoying but i am trying to implement your solution and i can't do it with success.

Can you give me an example of your solution?

Thanks in advance!

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Xilinx Employee
Xilinx Employee
9,530 Views
Registered: ‎08-13-2007

Re: post-route simulation with jitter

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It isn't my solution, but I've seen this approach suggested before.

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;

entity JITTER_TB is
end JITTER_TB;

architecture TB of JITTER_TB is
  constant tHCLK:TIME:=1000 ps; -- 500.0 MHz
  constant tJMAX:TIME:=100 ps;  -- maximum jitter amplitude
  signal CLK:STD_LOGIC:='1';    -- clean clock
  signal CLKJ:STD_LOGIC;        -- jittery clock
begin
-- clean clock
  CLK<=not CLK after tHCLK;
-- clock with jitter
  process
    variable Seed1:INTEGER:=1234;
    variable Seed2:INTEGER:=5678;
    variable R:REAL:=0.0;
  begin
    CLKJ<=transport CLK after R*tJMAX;
    UNIFORM(Seed1,Seed2,R);
    wait until CLK'event;
  end process;
end TB;

 

Cheers,

bt

 

-- credit to cb at xilinx

View solution in original post

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Visitor
Visitor
8,028 Views
Registered: ‎02-04-2009

Re: post-route simulation with jitter

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Thanks a lot for your answer!!! This approach seems fine to me at least for now.

 

I am thinking that another approach (more hardware solution for my problem) is to use PLLs (tha already exist in ise) since their outputs have some ammount of jitter and to connect  them at the clock inputs of my design. By this way the simple test bench  will work fine. I don't know if the approach i discuss is right, so I 'll try that  and if i succeed i will inform the forum.

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