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Saud
Newbie
Newbie
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Registered: ‎03-24-2020

problem in stimulation

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i have this pproject which is muliplayer and i have done all the modules and test it and all of them are work correctly individually but when i put them in one top level module the senthsizes is work perfect but when i try to simulate the top level module the output PRD and Result won't appears like what i want

this is the code

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    20:09:47 03/16/2020 
// Design Name: 
// Module Name:    firstPart 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Project1(PRD,Result,Y1,Y2,Y3,MN,MT,CLK,STA);

//output X0;
output [5:0] PRD, Result;
input CLK,STA;
input [5:0] MN;
input [2:0] MT;
output wire Y1,Y2,Y3;
wire X1;
ControlUnit module0(Y1,Y2,Y3,D0,D10,X1,CLK,STA);
dataPathUnit module1(PRD,Result,X1,Y1,Y2,Y3,MN,MT,D0,D10,CLK);

endmodule
//--------------------------------------------------------------------------------------
//######################################################################################
//######################################################################################
//################################# Control Unit #######################################
//######################################################################################
//######################################################################################
//------------------------------------------------------------------------------
module ControlUnit(Y1,Y2,Y3,D0,D10,X1,CLK,RES);

input CLK,RES,X1;
output Y1,Y2,Y3,D0,D10;
wire [3:0] wire1;
wire wire3, X1not;
wire [10:0] wire2;

counter counter0(wire1,CLK,RES);
decoder_4x16 decoder(wire2,wire1);

or or0(wire3,wire2[1],wire2[4],wire2[7]);
not (X1not,X1);
and and0(Y1not,X1not,wire3);
and and1(Y1,X1,wire3);

or or1(Y2,wire2[2],wire2[5],wire2[8]);

or or2(Y3,wire2[3],wire2[6],wire2[9]);

assign D0=wire2[0];
assign D10=wire2[10];

endmodule

//--------------------------------------------------------------------------------
module counter(dout,CLK,RES);
input CLK,RES;
output [3:0] dout;
wire not0_out,not1_out,not2_out,not3_out,not4_out,not6_out,not5_out;

not not0(not0_out,dout[0]);
not not1(not1_out,dout[0]);
not not2(not2_out,dout[1]);
not not3(not3_out,dout[1]);
not not4(not4_out,dout[2]);
not not5(not5_out,dout[2]);
not not6(not6_out,dout[3]);
FlipFlop dff0(dout[0],  not0_out  ,CLK,       RES);
FlipFlop dff1(dout[1],  not2_out  ,not1_out,  RES);
FlipFlop dff2(dout[2],  not4_out  ,not3_out,  RES);
FlipFlop dff3(dout[3],  not6_out  ,not5_out,  RES);
 
endmodule

//--------------------------------------------------------------------------------------
module FlipFlop(Qout,Datain,CLK,RES);

input RES,Datain,CLK;
output  reg Qout;

always @(posedge RES or posedge CLK)
if(RES)
	Qout=1'b0;
else
	Qout=Datain;

endmodule


//---------------------------------------------------------------------------------------
module decoder_4x16 (Dout,Datain);

input [3:0]Datain;
output reg [15:0] Dout;
integer i;


always @(Datain)
for (i=0; i<=15; i=i+1) 
if(Datain == i) 
 Dout[i] = 1'b1;
else 
 Dout[i] =1'b0;


endmodule
//--------------------------------------------------------------------------------------
//######################################################################################
//######################################################################################
//############################## Data Path Unit ########################################
//######################################################################################
//######################################################################################
//--------------------------------------------------------------------------------------
module dataPathUnit(PRD,Result,X1,Y1,Y2,Y3,MN,MT,D0,D10,CLK);

inout [5:0] PRD;
output [5:0] Result;
output X1;
input [5:0] MN;
input [2:0] MT;
inout Y1, Y2, Y3, D0;
input D10, CLK ;
wire [5:0] wire0, wire1 ;



multiplayer module0(X1,D0,MT,CLK,Y2);
Multiplicand module1(wire0,D0,MN,CLK,Y3);
adder module2(wire1,PRD,wire0);
product module3(PRD,wire1,Y1,CLK,D0);
result module4(Result,PRD,D10,CLK,D0);

endmodule

//--------------------------------------------------------------------------------
module multiplayer(X1,LOAD,MT,CLK,Y2);

output X1;
input [2:0] MT;
input CLK,Y2,LOAD;
reg [2:0] MTQ;

always@(negedge CLK)
	begin
		if (LOAD)
			MTQ<=MT;
		else if (Y2)
			MTQ<=MTQ>>1;
	end
	
	assign X1=MTQ[0];
	
endmodule

//--------------------------------------------------------------------------------
module Multiplicand(Qout,LOAD,MN,CLK,Y3);

output reg [5:0] Qout;
input  [5:0] MN;
input LOAD,CLK,Y3;

always@(negedge CLK ) 
	begin 
		if (LOAD) 
			Qout<=MN;
		else if (Y3)
			Qout<=Qout<<1;
		end
	
endmodule

//----------------------------------------------------------------------------------
module adder(Qadd,Dpro,Dmul);

output reg [5:0] Qadd;
input [5:0] Dpro, Dmul;

always@(Dmul,Dpro)
	begin
		Qadd=Dpro+Dmul;
	end
	
endmodule

//----------------------------------------------------------------------------------
module product(PRD,datain,Y1,CLK,D0);

output reg [5:0] PRD;
input [5:0] datain;
input CLK,Y1,D0;

always @(negedge CLK or posedge D0)
	begin
		if (D0)
			PRD<=0;
		else if (Y1)
			PRD<=datain;

	end
	
endmodule

//---------------------------------------------------------------------------------
module result(Result,datain,D10,CLK,D0);

output reg [5:0] Result; 
input CLK, D10, D0;
input [5:0] datain;

always @(negedge CLK or posedge D0)
begin
	if (D0)
		Result<=0;
	else if (D10)
		Result<=datain;
end


endmodule
 

it is devided into two part control unit and data path unit and each unit devided into sevral unit

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Saud
Newbie
Newbie
339 Views
Registered: ‎03-24-2020

i change the counter from using module Dflipflop to non module in otherword i used always (sequential) and the CLK in simulate begin with 1 instead of 0 and the same for reset(RES or STA)

 

 

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Saud
Newbie
Newbie
388 Views
Registered: ‎03-24-2020

this is the diagram i tried to do,

the adder is without carry in and without carryout

control unit send D0,D10,Y1,Y2 and Y3 to datapath

Annotation 2020-03-24 191835.png
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Saud
Newbie
Newbie
340 Views
Registered: ‎03-24-2020

i change the counter from using module Dflipflop to non module in otherword i used always (sequential) and the CLK in simulate begin with 1 instead of 0 and the same for reset(RES or STA)

 

 

View solution in original post

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