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Observer
Observer
5,839 Views
Registered: ‎08-01-2008

problem in writing my test vectors in a file

hi all:

 

I am trying to read and write test vectors from a file.

the reading process is working fine and it reads correctly from the input file.

the problem is; the writing operation is not working at all. I don't what is the reason; 

 

 

herein my code

 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_textio.all;
use STD.textio.all;

ENTITY testbench IS
generic (m: positive := 3);
END testbench;
 
ARCHITECTURE behavior OF testbench IS
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Multiplier
  generic (m: positive);
    PORT(
         clk : IN  std_logic;
         load : IN  std_logic;
         reset : IN  std_logic;
         shift : IN  std_logic;
         a : IN  std_logic_vector((m-1) downto 0);
         b : IN  std_logic_vector((m-1) downto 0);
         p : IN  std_logic_vector((m-1) downto 0);
         c : OUT  std_logic_vector((m-1) downto 0)
        );
    END COMPONENT;

 --- function for converting string to std_logic_vector ---
 function str_to_stdvec(input:string)return std_logic_vector is
  variable temp: std_logic_vector(input'range) := (others => 'X');
 begin
  for i in input'range loop
   if (input(i) = '1') then
       temp(i) := '1';
   elsif (input(i) = '0') then
        temp(i) := '0'; 
   end if;
  end loop;
  return temp;
 end function str_to_stdvec;

--- function for converting std_logic_vector to string ---
 function stdvec_to_str(input:std_logic_vector)return string is
  variable temp: string(input'range) ;--:= (others => 'X')--input'left+1 downto 1
 begin
  for i in input'reverse_range loop
   if (input(i) = '1') then
       temp(i+1) := '1';
   elsif (input(i) = '0') then
        temp(i+1) := '0';
           else
               temp(i+1) := 'x';  
   end if;
  end loop;
  return temp;
 end function stdvec_to_str;  

   -- Inputs of multiplier --
   signal clk : std_logic := '0';
   signal load : std_logic := '0';
   signal reset : std_logic := '0';
   signal shift : std_logic := '0';
   signal a : std_logic_vector((m-1) downto 0) := (others => '0');
   signal b : std_logic_vector((m-1) downto 0) := (others => '0');
   signal p : std_logic_vector((m-1) downto 0) := (others => '0');

  -- Outputs of multiplier --
   signal c : std_logic_vector((m-1) downto 0);
   --signal c_sig : std_logic_vector((m-1) downto 0);
   --Constant--
 constant t : time := 100 ns;
 


BEGIN

 -- Instantiate the Unit Under Test (UUT)
   uut: Multiplier
 Generic map (m => m)
 PORT MAP (
          clk => clk,
          load => load,
          reset => reset,
          shift => shift,
          a => a,
          b => b,
          p => p,
          c => c
        );
--c_sig<=c;

CLK <= not CLK after t/2;
reset<='1',
   '0' after t;
load<='0',
      '1' after t,
  '0' after (2*t);
shift<='0',
   '1' after (2*t),
   '0' after ((2+m)*t);
--a<="101";
--b<="011";
--p<="011";

 


 read_input: process
        file infile: text;
        variable a_input_str: string(m downto 1);
        variable b_input_str: string(m downto 1);
    variable p_input_str: string(m downto 1);
    variable a_input: std_logic_vector((m-1) downto 0);
        variable b_input: std_logic_vector((m-1) downto 0);
    variable p_input: std_logic_vector((m-1) downto 0);
    variable file_line: line;
   begin
        file_open(infile, "infile.txt", READ_MODE);
    wait until rising_edge(clk);
        while not endfile(infile) loop
            readline (infile, file_line);
    read(file_line, a_input_str);
    readline (infile, file_line);
    read(file_line, b_input_str);
    readline (infile, file_line);
    read(file_line, p_input_str);
    a_input := str_to_stdvec(a_input_str);
    b_input := str_to_stdvec(b_input_str);
    p_input := str_to_stdvec(p_input_str);
    a <= a_input;
    b <= b_input;
    p <= p_input;
   wait until falling_edge(clk);
   end loop;
         file_close(infile);
   end process read_input;

--wait for 500 ns;

write_input: process 
--        file outfile : TEXT open WRITE_MODE is "outfile.txt";
    file outfile: text;
        variable output_str: string(m downto 1);--:="101"
    variable output: std_logic_vector((m-1) downto 0);--:="101"
    variable file_line: line;
   begin
        file_open(outfile, "outfile.txt", WRITE_MODE);--infile.txt
    wait until rising_edge(clk);
        while not endfile(outfile) loop
    output := c;
    output_str := stdvec_to_str(output);
    write(file_line, output_str);
    writeline (outfile, file_line);
        
   wait until falling_edge(clk);
   end loop;
         file_close(outfile);
   end process write_input;

 


END behavior;

I am asking if any thing i did not do or missing in my code;

if so how can I sort out this problem;

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5 Replies
Highlighted
Xilinx Employee
Xilinx Employee
5,818 Views
Registered: ‎08-15-2007

Re: problem in writing my test vectors in a file

Hello,

 

I couldn't find anything particularly wrong with your code.  Can you zip up the design files and attach it to the thread so myself and other forum members can give it a go and see if we catch anything?  

 

Thanks.

Eddie
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Highlighted
Observer
Observer
5,807 Views
Registered: ‎08-01-2008

Re: problem in writing my test vectors in a file

many thanks for the reply;

attached the zipped files;

many thanks in advance;

cheers 

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Highlighted
Xilinx Employee
Xilinx Employee
5,787 Views
Registered: ‎08-15-2007

Re: problem in writing my test vectors in a file

Though I'm not quite certain what's wrong with your code, I was able to "fix" it by making the following changes:

 

write_input: process 
--        file outfile : TEXT open WRITE_MODE is "outfile.txt";
          file outfile: text;
        variable output_str: string(m downto 1);--:="101"
          variable output: std_logic_vector((m-1) downto 0);--:="101"
          variable file_line: line;
   begin
        file_open(outfile, "outfile.txt", WRITE_MODE);--infile.txt
    wait until rising_edge(clk);
        --while not (endfile(outfile)) loop
    while true loop
       
                output := c;
                --output_str := stdvec_to_str(output);
                --write(file_line, output_str);
                write(file_line, output);
                writeline (outfile, file_line);
           
            wait until falling_edge(clk);
            end loop;
         file_close(outfile);
   end process write_input;

 

You may want to review the sizes of your variables in the function stdvec_to_str which you declare earlier.  I'm not quite sure why the while loop does not work ... so a quick fix is to use "while true loop".

 

Sorry I couldn't spend more time looking at your code, hope the fix gets you going.  Maybe another forum member can chime in on what they think is wrong with your original HDL.

Eddie
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Highlighted
Observer
Observer
5,776 Views
Registered: ‎08-01-2008

Re: problem in writing my test vectors in a file

thanks any way edv for your time;

I will work out with it and I will come back soon.

cheers

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Anonymous
Not applicable
5,756 Views

Re: problem in writing my test vectors in a file

Perhaps because you are always at the end of an outfile?

 

"while not endfile(infile)" is obviously useful, but what does "endfile" mean on an outfile?

You want to loop until you have run out of INPUT data, not OUTPUT file...

 

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