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Explorer
Explorer
1,299 Views
Registered: ‎08-16-2017

problems with behavioral simulation

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Hello guys,

 

In the behavioral simulation of my design all the signals are in high Z state or meta stable state.

I don't know what if there is a problem with my design, test bench or the simulator.

I have attached the log file. I don't see any errors and warnings in the log file.

In the message window, I see the warning -

[filemgmt 20-736] The current top specification, "Top_design" (Library: xil_defaultlib), does not uniquely identify a single design element. Using "Top_design" (Library: xil_defaultlib, File: C:/Users/vivek/krylov/Krylov.srcs/sources_1/new/Top_design.v).

Please let me know what can be an issue here.

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1 Solution

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Xilinx Employee
Xilinx Employee
1,878 Views
Registered: ‎08-10-2015

Re: problems with behavioral simulation

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Hi Vivek.

 

I not seeing 'Z' or meta-data stage with the design files that you have shared. Simulation is working fine.

Please find the attached screenshot.

 

 

As per my understanding you are running simulation with out adding testbench files to design sources. Please add sim_kry.v file to deisgn sources and set it as top module then run simulation.

 

 

Thanks,

Sunilkumar

sim_screenshot.PNG
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5 Replies
Xilinx Employee
Xilinx Employee
1,296 Views
Registered: ‎08-10-2015

Re: problems with behavioral simulation

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Hi @vivek,

 

 

Can you please share design files ?

 

 

Thanks,

Sunilkumar

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Explorer
Explorer
1,286 Views
Registered: ‎08-16-2017

Re: problems with behavioral simulation

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Hi @sunilku -

Sure!

I have attached the design and test bench files.

Top_design is the top module which wraps up all the submodules.

 

Thank you.

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Xilinx Employee
Xilinx Employee
1,879 Views
Registered: ‎08-10-2015

Re: problems with behavioral simulation

Jump to solution

Hi Vivek.

 

I not seeing 'Z' or meta-data stage with the design files that you have shared. Simulation is working fine.

Please find the attached screenshot.

 

 

As per my understanding you are running simulation with out adding testbench files to design sources. Please add sim_kry.v file to deisgn sources and set it as top module then run simulation.

 

 

Thanks,

Sunilkumar

sim_screenshot.PNG
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Explorer
Explorer
1,269 Views
Registered: ‎08-16-2017

Re: problems with behavioral simulation

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Hi @sunilku -

 

Thank you for your help! 

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Explorer
Explorer
1,260 Views
Registered: ‎08-16-2017

Re: problems with behavioral simulation

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Hi @sunilku.

 

Just a quick question. When I go for the synthesis of the design, it shows the number of bonding IOBs = 114.

But, the IOB of the top design is 290!

Also, in the log file it says that it has overutilized the DSP blocks. DSP blocks utilized is 707 but available 240!

Is there a way where I can use the LUTs to accomodate the rest of the design?

 

Please let me know. Thank you.

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