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Observer bondylep
Observer
799 Views
Registered: ‎10-09-2018

processor reset module produce to add_1 must be in the range error

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Hi, I design a bd with zynq 7000, i found that once the processor reset module is instantiated, the reset output port will first not reset, then reset, when reset after one cycle, then will error show axi utils add_1 must be in the range, becase this is encrypted code ,i can't figure out why will happen, but i saw the waveform ,the m_01 axi bus valid single have X.

what can I do ,i want use the processor reset module, but can not simulate.

How can i debug with the encrypted module. is the axi interconnect should be reset first,otherwise will error.

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
747 Views
Registered: ‎07-16-2008

Re: processor reset module produce to add_1 must be in the range error

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The error message is coming from the assertion in AXI SRL FIFO (encrypted) used within the IP core.

This kind of failure is typically seen when master and slave AXI are not initialized. e.g. when the slave TVALID and TDATA are in an 'U' or 'X' state.
The unknown or undefined state applied to the core cause the assertions in the AXI SRL FIFO to be triggered, which terminates the simulation.
 
You need to firstly examine the testbench (or the AXI bus drivers) and ensure they're all initialized.
For instance,
  -- Data slave channel signals
  signal s_axis_data_tvalid              : std_logic := '0';  -- payload is valid
  signal s_axis_data_tready              : std_logic := '1';  -- slave is ready
  signal s_axis_data_tdata               : std_logic_vector(15 downto 0) := (others => '0');  -- data payload
 
  -- Data master channel signals
  signal m_axis_data_tvalid              : std_logic := '0';  -- payload is valid
  signal m_axis_data_tdata               : std_logic_vector(23 downto 0) := (others => '0');  -- data payload
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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7 Replies
Moderator
Moderator
774 Views
Registered: ‎09-15-2016

Re: processor reset module produce to add_1 must be in the range error

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Hi @bondylep,

 

Are you facing the below error?

Failure: ERROR:add_1 must be in range [-1,DEPTH-1]

 

Can you please check if the following posts helps:

https://forums.xilinx.com/t5/Simulation-and-Verification/Vivado-simulation-error-2016-2-Failure-ERROR-add-1-must-be-in/td-p/726240 

https://forums.xilinx.com/t5/Simulation-and-Verification/vivado-2015-1-simulation-error-Failure-ERROR-add-1-must-be-in/td-p/600653

 

Thanks & Regards,
Sravanthi B
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Observer bondylep
Observer
758 Views
Registered: ‎10-09-2018

Re: processor reset module produce to add_1 must be in the range error

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I have read all the related post, and I  run the base zynq project, it is ok, i think it is not the reset module problem, maybe it is my IP problem, but i forced all the axi related x signal, it is still error. I have no other choice.

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Observer bondylep
Observer
752 Views
Registered: ‎10-09-2018

Re: processor reset module produce to add_1 must be in the range error

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i worried about my IP, i used the VIP to drive my IP, i force the rst to low once simulation start, then the error disappear,  but the base zynq example project is the same reset module ,it is ok, the only difference is that, the axi sinal is U in good example project ,but in my proect it is X, so i worried about my IP, i can not know the root cause。

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Xilinx Employee
Xilinx Employee
748 Views
Registered: ‎07-16-2008

Re: processor reset module produce to add_1 must be in the range error

Jump to solution

The error message is coming from the assertion in AXI SRL FIFO (encrypted) used within the IP core.

This kind of failure is typically seen when master and slave AXI are not initialized. e.g. when the slave TVALID and TDATA are in an 'U' or 'X' state.
The unknown or undefined state applied to the core cause the assertions in the AXI SRL FIFO to be triggered, which terminates the simulation.
 
You need to firstly examine the testbench (or the AXI bus drivers) and ensure they're all initialized.
For instance,
  -- Data slave channel signals
  signal s_axis_data_tvalid              : std_logic := '0';  -- payload is valid
  signal s_axis_data_tready              : std_logic := '1';  -- slave is ready
  signal s_axis_data_tdata               : std_logic_vector(15 downto 0) := (others => '0');  -- data payload
 
  -- Data master channel signals
  signal m_axis_data_tvalid              : std_logic := '0';  -- payload is valid
  signal m_axis_data_tdata               : std_logic_vector(23 downto 0) := (others => '0');  -- data payload
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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Observer bondylep
Observer
680 Views
Registered: ‎10-09-2018

Re: processor reset module produce to add_1 must be in the range error

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why the example project is also U, it is ok, can you help to debug my project? if it is ok ,i will attach it

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Observer bondylep
Observer
605 Views
Registered: ‎10-09-2018

Re: processor reset module produce to add_1 must be in the range error

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can you tell me which module will instaniate the axi_utils, because my project is so big, all module interface used axi interface, i can not locate which moduel cause the error.

which axi cause the error, axi or axis? 

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Observer bondylep
Observer
515 Views
Registered: ‎10-09-2018

Re: processor reset module produce to add_1 must be in the range error

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I finally use exclusive methord to loace the error is in the FFT IP,  i guess that the error trigger condition maybe wrong, it is the s_axis_valid should not be X, but in my Zynq system simulation,  the process rst module will not reset when simulation start up, so all singnal will X include the s_axis_valid.

Suggestion: the IP code could be encypted, but why the path also encrypted, this is not user friendly,I take about one week to locate the module which trigger the error.

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