cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
404 Views
Registered: ‎07-18-2018

"The Project's Simulator Language setting and the behavioral simulation model language of the following IP are incompatible." Warning when generating output Products

I have a clock wizard. I made a change to the wizard, and wanted to see the updated .vho file.
 
The IP is incontext. But when I generate output products to get the inst. tempates i see the following pop up:
 
 
The Project's Simulator Language setting and the behavioral simulation model language of the following IP are incompatible. The behavioral simulation may fail to elaborate.
 
<Clock Wizard IP>
 
Turn on Out-of-context settings for the IP listed above to automatically use a structural simulation netlist model instead.
 
I can contiune, an di get what I want. But my project language is VHDL or Verilog, and my Simulator is Mixed (Vivado Sim) and no combination of settings make this go away.
 
Two questions:
 
1. What does this message actually mean? What is it trying to tell me?
 
2. How do I make it go away without using OOC. I don't need this simple MMCM to be an OOC IP.
 
Thanks,
 
Evan
0 Kudos
1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
351 Views
Registered: ‎07-16-2008

回复: "The Project's Simulator Language setting and the behavioral simulation model language of the following IP are incompatible." Warning when generating output Products

Hi Evan,

I cannot reproduce the message at my end. Simulator language is set to 'Mixed'. Project language is set to either 'VHDL' or 'Verilog'. I gave it a try in 2018.2 and 2018.3.

What is your Vivado release and Clocking Wizard IP version?

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos