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eestar
Participant
Participant
2,816 Views
Registered: ‎08-21-2012

read latency in block ram(named_funcsim.v) simulation is 2, should be 3

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Hi,

I generate a block ram memory IP in vivado, read latency is 3. When simulate with named_funcsim.v, see the read latency is 2; but it is 3 when using ../sim/name.v and ../blk_mem_gen_v8_2/simulation/blk_mem_gen_v8_2.v. After implementation, it is also 3.

I am using vivado 2015.2 and Questasim, the verilog timescale is 1ps/1ps.

 

Can I use named_funcsim.v when run functional simulation? I like this file, just one file for one IP. If can use, why read latency did not match? Thanks for any help!

 

 

BR

Guoxing

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florentw
Moderator
Moderator
4,702 Views
Registered: ‎11-09-2015

Hi @eestar,

 

Could you try to add some delay between your clock and your signals in the tb?

 

My guess is that you see only 2 latency because the data are captured directly

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
Moderator
Moderator
4,703 Views
Registered: ‎11-09-2015

Hi @eestar,

 

Could you try to add some delay between your clock and your signals in the tb?

 

My guess is that you see only 2 latency because the data are captured directly

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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eestar
Participant
Participant
2,769 Views
Registered: ‎08-21-2012

@florentw, Thank you very much for the help!

After adding delay, the latency is right, it 3.

And after rechecking the code, found another code error, in my code, the the ram address is driven by a sequence logic, but using blocking assignments(=), this should be the root cause this delay mismatch. After changing to Nonblocking assignments(<=), the latency is right without verilog delay.

 

BR

Guoxing

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