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Anonymous
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rising_edge event in VHDL not working properly in Isim simulator

Hi,

 

           I have instanciated two components (chol2 and dInputController) and 32 bit float point divider IP in testbench_chol2.vhd.

The file dInputController has a FSM designed, which is such that present_state changes only on rising_edge event on 'not_output_ack' signal. The value of the signal 'gInput' changes based on a MULTIPLEXER select signal input 'mux_sel_g'. This 'mux_sel_g' changes based on 'present_state'. But in the output timing diagram generated by ISim Simulator, it looks like the signal 'gInput' {or inturn the signal 'present_state'} changes at some other instant instead when rising_edge event happens on ''not_output_ack' ' signal.


I have atached the timing diagram pic which shows the above described malfunction.

Why is it happening? Help me.

 

Regards

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6 Replies
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Moderator
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Registered: ‎07-01-2015

Re: rising_edge event in VHDL not working properly in Isim simulator

Hi @Anonymous,

 

Please try the following modifications in dcalculatorInputController.vhd:

Replace

 

process(reset,not_output_ack)
begin
if reset = '1' then
present_state <= S0;
elsif rising_edge(not_output_ack) then
present_state <= next_state;
end if;
end process;

 

by

 

 

if rising_edge(not_output_ack) then
if reset = '1' then
present_state <= S0;
else
present_state <= next_state;
end if;
end if;
end process;

 

Happy New Year!

 

Thanks,
Arpan

 

Thanks,
Arpan
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Anonymous
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Re: rising_edge event in VHDL not working properly in Isim simulator

Hi,

     Happpy New Year. 

    Yeah, I changed as you said and the timing diagram is again the same thing as previous and has not improved. Both the code (yours and mine) must get triggered at rising_edge of the signal. But happens at random instant? Did it work in your case? I mean ,is my installation not proper/complete?

 

 

I am attaching the new timing diagram after the suggested code change. Plesae look into it.

 

 

 

Regards

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Moderator
Moderator
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Registered: ‎07-01-2015

Re: rising_edge event in VHDL not working properly in Isim simulator

Hi @Anonymous,

 

According to my understanding:

gInput is o/p of dInputcontroller and i/p to SUB1 which are operating at different clocks i.e.; clk and not_output_ack.

That may be causing this issue. I am not sure about your requirements but mapping clk of cholsky2 and not_output_ack of dinputcontroller to same signal on test bench I am getting below results.

 

Thanks,
Arpan

Thanks,
Arpan
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Anonymous
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Re: rising_edge event in VHDL not working properly in Isim simulator

Hi,

    Yeah your understanding about my code is correct and thank you for trying. 

    By replacing 'not_output_ack' with 'clk' in dinputcontroller PORT MAP ,  still the 'present_state' doesn't change at rising_edge of 'clk' signal . This what I infer from the attached picture . And more over 'clk' and 'not_output_ack' signals operating at different rate shouldn't have problem at the point where rising_edge of 'not_output_ack' needs to detected by the simulator. In case a problem is to happen for the reason that they operate at different arte, it must be for the subtractor output na?

 

Regards

   

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Registered: ‎07-01-2015

Re: rising_edge event in VHDL not working properly in Isim simulator

Hi @Anonymous,

 

I am not sure of the complete logic of your design.

I prepared  a small test case to debug dcalculatorInputController individually.

It's working at rising_edge of not_output_ack.

 

Hope this will be helpful.

 

Thanks,
Arpan

Thanks,
Arpan
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Anonymous
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Re: rising_edge event in VHDL not working properly in Isim simulator

Hi @arpansur,

 

                   Thank you so much for the test bench. Yeah, the rising_edge on the new 'not_output_ack' signal is getting detected

I guess you have ANDed th 'clk' signal and old ''not_output_ack' ' signal to get new ''not_output_ack' ' signal.n I tried the same thing with my complete design(all mathematical function IPs included with chol2 file). In this case it is not working. I find no point in this. When a entity which can take I/P is included in the design(chol2 in this case), the device controlling the O/P is not working properly.

 

Yeah, let me tell my requirement.


The design in chol2 does this:

d(n) = gInput - {w(1)*w(1)*d(1) + w(2)*w(2)*d(2) + ........... w(n-1)*w(n-1)*d(n-1)}

 

1) Initially a pre fixed value d(1) is stored directly in address "00" in BRAM inside chol2 entity
2) w(1) = k/d(1) is calcuated and given to chol2. w(1) is output of divider (here k is inputDIV1 in design)
3) Calculate d(2) using above equation in chol2 and store it in address "01"
4) w(2) = k/d(2) is generated and given to chol2. w(2) is output of divider (here k is inputDIV1 in design)
5) Calculate d(3) using above equation in chol2 and store it in address "10"
and proceed till finding d(4).

 

On the whole, my aim is to calculate d(1), d(2), d(3) and d(4) and w(1), w(2), w(3). This is  actually a part of LDL' decomposition technique'.

 

For each d(n) calculation, gInput is differenet(a22, a33, a44 signals in my design in dInputController.vhd file)
I mean, when n = 2, gInput = a22,
             when n = 3, gInput = a33;
             when n = 4, gInput = a44;

 

This genration of gInput and external_address_output (address where d(n) is stored as described in steps 1,3 and 5) dInputController.vhd is where the problem is happening.

 

Hope my explanation fine. I am ready to provide more information if it is un satisfactory for you.

Thanks again for your files.

 

Regards

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