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Visitor
Visitor
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Registered: ‎06-21-2012

shift register problem

Hi,

 

I have a strange problem with shift registers matrix simulation. This is the code:

 

module shift_matrix

(clk, en_shift_ver, en_shift_hor_sx, data_in,
data_out_r0, data_out_r1, data_out_r2, data_out_r3,
data_out_r4, data_out_r5, data_out_r6, data_out_r7,
data_out_r8, data_out_r9, data_out_r10, data_out_r11,
data_out_r12, data_out_r13, data_out_r14, data_out_r15,
data_out_r16, data_out_r17, data_out_r18);

parameter shift_sx_cycles = 162;
parameter vertical_width = 19;
parameter data_out_width = 19;

 

input clk, en_shift_ver, en_shift_hor_sx;
input [shift_sx_cycles-1:0] data_in;
output [data_out_width-1:0] data_out_r0;
output [data_out_width-1:0] data_out_r1;
output [data_out_width-1:0] data_out_r2;
output [data_out_width-1:0] data_out_r3;
output [data_out_width-1:0] data_out_r4;
output [data_out_width-1:0] data_out_r5;
output [data_out_width-1:0] data_out_r6;
output [data_out_width-1:0] data_out_r7;
output [data_out_width-1:0] data_out_r8;
output [data_out_width-1:0] data_out_r9;
output [data_out_width-1:0] data_out_r10;
output [data_out_width-1:0] data_out_r11;
output [data_out_width-1:0] data_out_r12;
output [data_out_width-1:0] data_out_r13;
output [data_out_width-1:0] data_out_r14;
output [data_out_width-1:0] data_out_r15;
output [data_out_width-1:0] data_out_r16;
output [data_out_width-1:0] data_out_r17;
output [data_out_width-1:0] data_out_r18;

wire [data_out_width-1:0] data_out [vertical_width-1:0];
reg [shift_sx_cycles-1:0] shift_reg [vertical_width-1:0];

genvar i;
generate
for (i=0; i < vertical_width; i=i+1)
begin: shift
always @(negedge clk)
if (en_shift_ver)
if (i == 0)
shift_reg[i] <= data_in;                      //DATA LATCH ON FIRST SHIFT REG
else
shift_reg[i] <= shift_reg[i-1];           // VERTICAL SHIFT OF ALL SHIFT REGS
else if (en_shift_hor_sx)
shift_reg[i] <= {shift_reg[i][shift_sx_cycles-2:0], shift_reg[i][shift_sx_cycles-1]};   //HORIZONTAL 1bit SHIFT 

assign data_out[i] = shift_reg[i][shift_sx_cycles-1:shift_sx_cycles-data_out_width];
end
endgenerate

assign data_out_r0 = data_out[0];
assign data_out_r1 = data_out[1];
assign data_out_r2 = data_out[2];
assign data_out_r3 = data_out[3];
assign data_out_r4 = data_out[4];
assign data_out_r5 = data_out[5];
assign data_out_r6 = data_out[6];
assign data_out_r7 = data_out[7];
assign data_out_r8 = data_out[8];
assign data_out_r9 = data_out[9];
assign data_out_r10 = data_out[10];
assign data_out_r11 = data_out[11];
assign data_out_r12 = data_out[12];
assign data_out_r13 = data_out[13];
assign data_out_r14 = data_out[14];
assign data_out_r15 = data_out[15];
assign data_out_r16 = data_out[16];
assign data_out_r17 = data_out[17];
assign data_out_r18 = data_out[18];

endmodule

 

The vertical shift works correctly. When I try to shift horizzontally if I set "parameter shift_sx_cycles = 162;" I have strange problem... some shift regs doesn't work for 4 clock cycle.

I attach a picture to explain. Can you help me??

21-06-2012 16-30-18.bmp
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