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Observer
Observer
2,742 Views
Registered: ‎05-03-2012

signal Connection in testbench

In my testbench, there are two modules.

.......

t1 uut1 (.a(a), .b(b), .c(c));

t2 uut2 (.a1(a), .b1(b), c1(c1));

........

c1 is the input for t2, and signal a, b is output signals. a, b is input signals for t1, c is output signal.

what type of signals  should I define the signals in order to connect the two modules?

Should I define a,b as wire?

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Moderator
Moderator
2,736 Views
Registered: ‎04-17-2011

Re: signal Connection in testbench

If a and b are not ports, you need to declare them as wire.

Do check the document: http://www.xilinx.com/support/documentation/application_notes/xapp199.pdf for writing effective testbenches.
Regards,
Debraj
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