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9,578 Views
Registered: ‎02-11-2015

signal delay problem in post route simulation

hello

when i try to simulate my design in poste route mode simulation in ISIM i encounter some problems,

the signal delays are not shown in the simulation

does any one knows how should i fix it?

 

 

thanks saber

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6 Replies
Teacher muzaffer
Teacher
9,569 Views
Registered: ‎03-31-2012

Re: signal delay problem in post route simulation

check to make sure you generated the SDF file correctly and it is being annotated on the design properly.

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9,564 Views
Registered: ‎02-11-2015

Re: signal delay problem in post route simulation

thanks for your answer and your time, i can see the generated file .sdf , but i dont it is generate correctely or not how can i add this file to ISIM

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9,563 Views
Registered: ‎02-11-2015

Re: signal delay problem in post route simulation

whats ur mean about annotated correctely?
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9,550 Views
Registered: ‎02-11-2015

Re: signal delay problem in post route simulation

when i simulate i see these erors how can i fix it??

 

ERROR: Can not find hierarchical name Maddsub_o1_mux0007_Madd_92_rt in the current scope. ERROR: SetupHold can not be annotated for Maddsub_o1_mux0007_Madd_92_rt. ERROR: Can not find hierarchical name Maddsub_o1_mux0007_Madd_92_rt in the current scope. ERROR: SetupHold can not be annotated for Maddsub_o1_mux0007_Madd_92_rt. ERROR: Can not find hierarchical name Maddsub_o1_mux0007_Madd_92_rt in the current scope. ERROR: SetupHold can not be annotated for Maddsub_o1_mux0007_Madd_92_rt. ERROR: Can not find hierarchical name Maddsub_o1_mux0007_Madd_92_rt in the current scope. ERROR: SetupHold can not be annotated for Maddsub_o1_mux0007_Madd_92_rt. ERROR: Can not find hierarchical name center1_5 in the current scope. ERmemvalue1_5.

...

 

WARNING: ISim could not properly annotate the SDF timing delay information.

 

 

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Teacher muzaffer
Teacher
9,528 Views
Registered: ‎03-31-2012

Re: signal delay problem in post route simulation

It seems that you have an SDF file but it's not being annotated properly. You need to figure out how $sdf_annotate is being called. You might need to add the proper --sdfroot to your compilation script. The errors you see suggest that annotation is not starting at the right point in hierarchy. Find out where Maddsub_o1_mux0007_Madd_92_rt is and add -sdfroot to that.
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Xilinx Employee
Xilinx Employee
9,495 Views
Registered: ‎08-01-2012

Re: signal delay problem in post route simulation

Whatversionoftools are you using?

 

In case of using VIvado 2012.X please refer http://www.xilinx.com/support/answers/54930.html 

 

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