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Visitor ifatm
Visitor
2,135 Views
Registered: ‎09-28-2017

simulation error [VRFC 10-149] using vivado 2017.2.1

Hi,

I have a .hdp project using a few libraries (containing .vhd files).

the .xpr project passed synthesis and implementation successfully.

However, when I try to simulate there is an error reffering me to the tcl console, there: [VRFC 10-149] saying that some external files arn't compiled in the major project library, and then the directory to the file is a different one.

looking at the .xpr file, those external files don't have an "ImportPath" as all imported sources do.

I have no idea why, I imported them regulary.

 

thank you,

Ifat

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5 Replies
Moderator
Moderator
2,072 Views
Registered: ‎09-15-2016

Re: simulation error [VRFC 10-149] using vivado 2017.2.1

Hi @ifatm,

 

Can you please share the complete error message.  Also, check in Libraries tab of Sources Window of Vivado GUI if you are observing the file .vhd under the library.

 

Is it possible to share your project to reproduce the issue and check.

 

Regards,
Sravanthi B

 

Thanks & Regards,
Sravanthi B
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Visitor ifatm
Visitor
2,064 Views
Registered: ‎09-28-2017

Re: simulation error [VRFC 10-149] using vivado 2017.2.1

Hi Sravanthi,

The complete error message is: ERROR: [VRFC 10-149] 'spi_master' is not compiled in library fca_pl_lib [file directory of original library].

ERROR: [VRFC 10-149] 'bmc_rx' is not compiled in library line_codec_lib [file directory of original library]

** fca_pl_lib - main and original library.

** line_codec_lib - external library (under different directory).

**Those errors appeare for every external .vhd file.

 

All files (external and internal) appeare in the libraries tab under sources: design sources -> vhdl -> xil_default_lib.

 

The project is not mine to share so it's a bit problematic =\

 

thank you!

 

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Visitor ifatm
Visitor
2,023 Views
Registered: ‎09-28-2017

Re: simulation error [VRFC 10-149] using vivado 2017.2.1

x

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Moderator
Moderator
1,999 Views
Registered: ‎04-24-2013

Re: simulation error [VRFC 10-149] using vivado 2017.2.1

Hi @ifatm

 

I don't know why you are receiving the error message but you could try the following as a workaround

 

Use the launch_simulation -scripts_only command to generate the scripts to run simulaiton.

You can use launch_simulation -help to get the syntax for the type of simulation that you wish to run.

 

Then go to <project_dir>/<project_name>.sim/simset/synth(impl)/func(timing)/ and edit the PRJ file to include the package file for compilation.


After saving the modified PRJ file, manually run "compile.bat", "elaborate.bat" and "simulate.bat" from the command prompt to launch simulation.

 

Best Regards
Aidan

 

 

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Observer alexkroh
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Registered: ‎04-25-2015

Re: simulation error [VRFC 10-149] using vivado 2017.2.1

I had a similar issue. Changing the compile order of the IP files seems to have fixed it.

Perhaps "auto update and compile order" prevents this issue, but I had to turn it off because it was removing files from the build that were used in the block design within my IP. Synthesis would then complain that the file didn't exist (Vivado 18.2). 

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