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Adventurer
Adventurer
442 Views
Registered: ‎01-18-2019

simulation set - include IP cores manually?

Dear All,

I have read all there is (and I could find) about simulation sets and it is still not clear.

I understand what they are for, and I know I can choose to include all design source files automatically or I can add only the necessary ones manually.

But my IP cores are made up of several files - inspite Xilinx's effort to put them into one file. This makes the manual file addition tiresome.  Am I to know what files an IP core is made up of? Why not add just the testbench and the RTL file? All submodules should be added automatically to the simset. This is what common sense dictates, is it not?  I do not want to automatically include everything in every simset. What concept am I missing here?

Thank you

Miklos

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8 Replies
Moderator
Moderator
393 Views
Registered: ‎04-24-2013

Re: simulation set - include IP cores manually?

Hi @mbence76 ,

You can add the IP to your testbench by referencing the .XCI e.g looking at the clk_wiz_0.xci

Capture1.PNG

Then it can be simulated in the same way as any other file.

Capture.PNG

Have I misunderstood your requirements?

If you do not wish to use the .XCI file then there is also a functional simulation netlist in VHDL format provided in the generated output products for the IP

You can find this in the IP Sources tab

Best Regards
Aidan

 

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Adventurer
Adventurer
372 Views
Registered: ‎01-18-2019

Re: simulation set - include IP cores manually?

Hi @amaccre ,

I created a brand new project (to investigate this phenomena better) with one topmodule and two submodules.

One submodule (sub_1.sv)  holds a simple BRAM  IP core. 

I created a new simset and included sub_1.sv and the blk_mem_gen_0.xci files only.

(I admit, I added no testbench.sv  now.)

This is what I got in response. This is IP name "is already in use".

simset_file_already_exists.PNG

I admit I am not familiar with what "output files of an IP" mean. 

But my original question is more general than this with IP cores:   

Does it make any sense to include sub_1 without including the BRAM in it?

Does it make any sense to include anything anywhere without including their submodules automatically?

It would be like packing my pocket radio in a suitcase for a vacation without including the battery, the speaker, the electronics. What is the plain plastic housing good for? And I do not want to include my whole household automatically just to have my working pocket radio with me.  See the analogy?

 

This is what I have now:

simset_file_structure.PNG

I have not tried the simulation netlist in VHDL.

Thanks

Miklos

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Adventurer
Adventurer
360 Views
Registered: ‎01-18-2019

Re: simulation set - include IP cores manually?

I mean let's say adding an .xci file solves the problem for IPs ( so far I could not even add an .xci ),  but what if I have sub-sub-sub RTL modules written by me, and want to test them at different levels?  When I include sub_1,  then sub_sub_1, sub_sub_2 and sub_sub_sub_1, .._2, .._3 should also be included, because sub_1 is useless without them.

Miklos

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Adventurer
Adventurer
352 Views
Registered: ‎01-27-2008

Re: simulation set - include IP cores manually?

Hi Miklos,

I'll address some points from your posts by referencing them with >>, hopefully help.

>>This is what I got in response. This is IP name "is already in use".

If the file (xci or sv or whatever) is already included in the project, this is the message you get. How you organize the project into filesets is up to you (but also automatically handled by xilinx using default filesets. Bottom line: once a file is within the project, you can only include it (a file of the certain name) once. That is what tool complained about.

The project includes filesets.  Filesets can be determined (at the TCL shell) as follows (this shows a project with default filesets and one additional fileset, sim_2):

 

get_filesets 
sources_1 constrs_1 sim_1 sim_2

>> I admit I am not familiar with what "output files of an IP" mean. 

These are Xilinx - generated files derived from the XCI file. Including the XCI file is all that is required for simulation, implementation, synthesis.

>> Does it make any sense to include sub_1 without including the BRAM in it?

>> Does it make any sense to include anything anywhere without including their submodules automatically?

Not really; for simulation you need to instantiate all submodules of whatever you're simulating. 

Your subsystem testbench approach is correct and applicable.

>>When I include sub_1,  then sub_sub_1, sub_sub_2 and sub_sub_sub_1, .._2, .._3 should also be included, because sub_1 is useless without them.

Right.

>>But my IP cores are made up of several files - inspite Xilinx's effort to put them into one file.

All you need is the XCI... unless you're talking about your own IP, where, yes, you might need to include more files. 

>> problem for IPs ( so far I could not even add an .xci )

The primary reason you cannot add xci files is that it's already there (in the project).  You can see this perhaps best from the sources window, IP sources tab which should show all IP currently in the project. You can also run get_ips:

 

get_ips
dsp48_mult

 

 

>>I do not want to automatically include everything in every simset. 

It might lack elegance but you can. Once you have the top level indicated (a specific testbench) it should only reference needed files. Note that you can manage files in specific simsets referencing other forum posts:

https://www.xilinx.com/support/answers/64111.html

Have fun,

Jerry

 

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Adventurer
Adventurer
343 Views
Registered: ‎01-18-2019

Re: simulation set - include IP cores manually?

Hello Jerry,

thank you for your reply.

>If the file (xci or sv or whatever) is already included in the project, this is the message you get.

Of course my files are already in the project. Where else? I am trying to simulate a submodule in my project using an IP in that submodule. The module sub_1 is also in my project, but when I included it into the simset, it did not complain.

I can either "include" all design files or not:

2019-08-08c.PNG

If not, then I can only "add" files, I cannot just "include" them or "reference" them into the simset:

2019-08-08d.PNG

 

>Once you have the top level indicated (a specific testbench) it should only reference needed files.

How do I "reference" them?  The link only shows me what I already know and copypasted above. This is exactly what I did before getting the complaining window about trying to add the same file again.

Apperantly I am missing the point here.

Miklos

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Adventurer
Adventurer
330 Views
Registered: ‎01-18-2019

Re: simulation set - include IP cores manually?

I created a testbench file, and it "instantiates" the sub_1 module:

module tb_for_sub1 ();
...
logic clk=1;
always #5 clk++;
        
sub_1 inst_sub_1 (
            .clk,
            .din (i_data),
            .dout (o_data_1)
            );    

always begin
   ...
end

endmodule    

 

Is this not how to place a DUT in a testbench?

In the default sim_1 simset it has always worked.

 

This is what I have now:

2019-08-08a.PNG

 

2019-08-08b.PNG

What am I doing wrong?

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Adventurer
Adventurer
287 Views
Registered: ‎01-27-2008

Re: simulation set - include IP cores manually?

Hi @mbence76 ,

>Once you have the top level indicated (a specific testbench) it should only reference needed files.

So what I mean by this is that the dependency of files referenced (or dependencies) by the testbench is automatically handled by the parser.  As shown the top level tb does not call ew_card_top_wrapper.v so it's not part of the "needed files" for that simulation (sim_1). That's what I mean.

example.png

To accomplish this, when a file is added (or whenever you set a new top level module), vivado runs

update_compile_order -fileset <whatever fileset you want>

which sorts this out.

 

>> >If the file (xci or sv or whatever) is already included in the project, this is the message you get.

>> Of course my files are already in the project. Where else?

All I am saying is the message you receive is due to that issue.

 

>>If not, then I can only "add" files, I cannot just "include" them or "reference" them into the simset:

I tested something that works fine and might help. I was able to add files to a specific simset for each simulation fileset without the system complaining.

First I created a new simulation set "sim_2", then I added a file (update_compile_order is automatically generated after the add_files).

I was able to add files to specific sets, repeatedly, for a file:

create_fileset -simset sim_2
add_files -fileset sim_2 <path>/tb/mixer_tb.sv
update_compile_order -fileset sim_2
add_files -fileset sim_1 <path>/tb/mixer_tb.sv
update_compile_order -fileset sim_1

 

Best,

Jerry

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Adventurer
Adventurer
286 Views
Registered: ‎01-27-2008

Re: simulation set - include IP cores manually?

@mbence76 ,

>>What am I doing wrong?

Nothing really, perhaps the tool is limited to sim_1; I would try the command I showed you to add_files to the specific simset. Something like this:

add_files -fileset sub_set_1 <path to xci file>

Per my test it should not complain. In fact I just tried that with the second simset (sim_2) I created in my project and it worked. 

Try it out.

Jerry

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