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Observer alexrp92
Observer
384 Views
Registered: ‎07-16-2019

simulation signal

Hi all!

I am trying to simulate this configuration, the cocks work well. The problem comes when I try to follow a signal (which I force to take a value) in the AXI bus.

 

1) The first problem comes when I force the signal in the M_AXI_GPO of the processing system to the value 1234abab. This signal is followed by the system till the S_axi_gpio_0. In that IP (axi_gpio_0) the signal is lost and the output signals (gpio_io_o and gpio2_io_o ) are set to 0. Why? Should I do something to keep the signal across this IP?

Imagen4.png

2)Trying to simulate the other part of the circuit, I fixed the signal of the cfg_data (input of the axis constant IP). The signal has a value till the last module (axis_red_pitaya_dac_1) but i don't understand some points:

2.1 the dds compiler output was set to have 14 bits. Why in the simulation takes a value with 32 bits? 

2.2 Why the axis_combiner ip  shows in the simulationjust  the output of the first dds 

2.3 Why the simulation signal doesn't go throught the axis_red_pitaya_dac_1. 

Imagen5.png

Imagen3.pngsimul30_09.png

 

Thank you 

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10 Replies
Scholar drjohnsmith
Scholar
374 Views
Registered: ‎07-09-2009

Re: simulation signal

Great your simulating,

 

i would suggets the two most likely prpoblems could be,

a) is the gpio / AXI in reset

b) have you the right address for the gpio in the simulation.

 

 

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Observer alexrp92
Observer
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Registered: ‎07-16-2019

Re: simulation signal

Thanks for answering, about your suggestions:

 

a) is the gpio / AXI in reset

the axi_gpio, the axi interconnect and the axis combiner are conected to a low active reset (s_axi_aresetn) which is conected to the procesor system reset. (in the simulation this signal is set to 1). Besides, the AXI interconnect is working well so this might not be the problem.

b) have you the right address for the gpio in the simulation.

I am not sure about this point. The axi_gpio has an address for the register between 4200_0000 and 4200_0FFF, This one is the address where the data is loaded for a correct communication, isn't it? 

in the simulation, the axi bus for the processing system IP, the AXI interconnect IP and the processor system reset IP have and address of 32 bits meanwhile the axi GPIO IP has an address of 8 bits.How can I specify the correct address for the gpio module?

 Imagen1.png

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Scholar drjohnsmith
Scholar
309 Views
Registered: ‎07-09-2009

Re: simulation signal

As you say, on the AXI , everything is on the 32 bit address,

    so the register is maped to address between 4200_0000 and 4200_0FFF 

Sorry , I can't see your pictures, so I m guessing here.

   what address are you writting to / reading from for the GPIO ?

The GPIO has multipel registers inside, ocntroling things liek read pins, write to pins, turn pins tri state or not ,

   

    

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Observer alexrp92
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Registered: ‎07-16-2019

Re: simulation signal

the address og the axi gpio IP has 9 bits (s_axi_araddr[8:0]) meanwhile the axi interconnect IP has a M00_AXI_awaddr[31:0]. which is the bus connected to the gpio input..

THE GPIO is configured as dual channel and both channels are all outputs.

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Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: simulation signal

Sorry , I just cant see this GPIO in the diagram

If the address is4200_0000 and 4200_0FFF

you need to be reading and writting to 4200_0000 to 4200_0FFF

 

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Observer alexrp92
Observer
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Registered: ‎07-16-2019

Re: simulation signal

Yes, the address in the address editor is : axi_gpio_0  offset address  0x4200 0000 with a range of 4k.

In the simulation, I forced the write address of the master signal from the processing system, to be 4200 0000 and the value .WDATA  to be ababab11.

these values go throught the buses with no problem until they reach the AXI GPIO IP. In this block the slave bus at the input of the IP  has an address of only 9 bits. (I dont know why..) and the address goes to 000, the data is keeped in the input. In the output the gpio_io_o takes the default value.

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Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: simulation signal

try writting to address 4200 0002 and 4200 00004, with some data 0x55 say.

 

 

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Observer alexrp92
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Registered: ‎07-16-2019

Re: simulation signal

writing the address 4200 0002, in the s_axi of the GPIO bus the address is 002 (hex) so it mantains the address. but there is a problem inside this block. the info reach the input but it doesn't go to the output.

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Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: simulation signal

Thats great news,

atleast the AXI part is sending th ecorrect address to the correct part.

Sorry, Im still running blind here,

   is there a register you can write / read ?

 

What is the address map of the registers in side the gpio block ?

  Im guessing there are more than one,

  for instance if its this core your using

https://www.xilinx.com/support/documentation/ip_documentation/axi_gpio/v2_0/pg144-axi-gpio.pdf

You can only access the internal registers on a step of 4, ( 32 bits )

i.e. 0, 4 , 8, C , 10 , 14 etc.

see table 2.4

To make the port output, you need to write to address 4, the tri state register,

    then you can write to address 0,

having said that,

I'd have thought the GPIO would default ot output .

 

anyone else got any thoughts ?

 

 

 

 

 

 

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Observer alexrp92
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Registered: ‎07-16-2019

Re: simulation signal

First of all, thank you very much for your time trying to solve this problem.

atleast the AXI part is sending th ecorrect address to the correct part

Yes, but the address in the GPIO block has 9 bits, instead of 32 of the previous ones.  what happens if the address set in the processing system is 4200 0fff (which is the maximum possible) in that case the address will be bigger than the GPIO address...

is there a register you can write / read ?

Sorry, I don't know what are you trying to say, are you talking about the GPIO IP inside the block design? if it is, I can choose: the GPIO  width (i put 32 bits) default output value (i put 0x000ff198) and default tri state (i  put 0x0000 0000)  I check the enable dual channel checkbox and for the gpio2 i did the same.

What is the address map of the registers in side the gpio block ?

I uderstand that this address map is what is displayed in the address editor : i put offset address: 0x4200 0000; range 4k and high address 0x4200 0FFF

 You can only access the internal registers on a step of 4, ( 32 bits )

yes, I've already take it into account. 

0x0000 GPIO_DATA Channel 1 AXI GPIO Data Register.
0x0004 GPIO_TRI Channel 1 AXI GPIO 3-state Control Register.
0x0008 GPIO2_DATA Channel 2 AXI GPIO Data Register.
0x000C GPIO2_TRI Channel 2 AXI GPIO 3-state Control.

 

To make the port output, you need to write to address 4, the tri state register,

oK, So that info is not taken in the block design by the simulation, I have to make a test bench programmig all this stuff? I've just adding the signals and forcing some values in the data  bus. mabe this is the problem.. What do you think?

 

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