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Visitor justins
Registered: ‎03-13-2018

sometimes PLL will not re-lock after reset

The design I'm working on has 5 PLLs/MMCMs. They are all fed by an input clock from a BUFG. For the previous year, I've seen no issues related to this logic. The coverage includes my unit tests as well as a regression suite developed by our verification team.

We recently found a scenario where sometimes 1 or more PLLs will fail to re-lock after being reset. I don't believe we are violating any of the usage guidelines. The reset is asynchronous, and applied for >10 input clock periods, which is present and non-changing the entire time. 

I believe this is some kind of simulation model artifact. We had been using the 2016.4 version of the simulation libraries. When I update to 2018.3, the behavior changes (some PLLs that don't re-lock using 2016.4 will re-lock using 2018.3, but not all).

Additionally, if I change the PLL multiply and divide values, but keep the same ratio, the behavior changes (sometimes results in a re-lock, sometimes not)

Has anyone seen anything like this and/or can suggest next steps for debugging?



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Registered: ‎09-15-2016

Re: sometimes PLL will not re-lock after reset

Hi @justins,

Can you please let us know which device are you using?

Thanks & Regards,
Sravanthi B
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